From patchwork Wed Apr 3 18:02:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas Stach X-Patchwork-Id: 13616561 X-Patchwork-Delegate: kuba@kernel.org Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0688152E11 for ; Wed, 3 Apr 2024 18:02:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712167365; cv=none; b=KDanCH5B+o2YCfaPRjKlTdGDcrmaWsS9bwfEO/BrW+BDRXYVvWxFXVwqaMSISXo53v2o/1b8FnDIcZAC1Vb8gY/cKYccDbh5oMtd1Oo2mUydmMOGhnR/OAuVQ1Ekij00gs83/2y7MyuwjJ0Tqti9EiyZUdRzjdgJj8XmY21x7vY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712167365; c=relaxed/simple; bh=JdjwYqPhDf6w2ahYMzJ2MHjxXKvZXil2sc27dpJ3Ni8=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=p14iGhtAPtfMKHWKTBKf9Mg5EFc9nQZI6O6xW04TMJNuB2S7fEUd1E2kWW0TfDVBwpsq5mJ9G0qMDhBcVP86NAMYklZ8V7uNVQy3WWaEfNRmjWR0QNvtDP9MsTubVZfTbhc2liDjNT/4SlOKFDDjW9fCNkCZ4k1cvN5LGGaEnIk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1rs4wO-0008GA-WA; Wed, 03 Apr 2024 20:02:29 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1rs4wN-00AE7z-2M; Wed, 03 Apr 2024 20:02:27 +0200 From: Lucas Stach To: Woojung Huh , UNGLinuxDriver@microchip.com, Andrew Lunn , Florian Fainelli , Vladimir Oltean Cc: netdev@vger.kernel.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: [PATCH 1/3] net: dsa: microchip: lan9372: fix TX PHY access Date: Wed, 3 Apr 2024 20:02:24 +0200 Message-Id: <20240403180226.1641383-1-l.stach@pengutronix.de> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org On the LAN9372 the 4th internal PHY is a TX PHY instead of a T1 PHY. TX PHYs have a different base register offset. Signed-off-by: Lucas Stach --- drivers/net/dsa/microchip/lan937x_main.c | 3 +++ drivers/net/dsa/microchip/lan937x_reg.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c index b479a628b1ae..6a20cbacc513 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -55,6 +55,9 @@ static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg) u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE; u16 temp; + if (dev->info->chip_id == LAN9372_CHIP_ID && addr == 3) + addr_base = REG_PORT_TX_PHY_CTRL_BASE; + /* get register address based on the logical port */ temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2))); diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h index 45b606b6429f..7ecada924023 100644 --- a/drivers/net/dsa/microchip/lan937x_reg.h +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -147,6 +147,7 @@ /* 1 - Phy */ #define REG_PORT_T1_PHY_CTRL_BASE 0x0100 +#define REG_PORT_TX_PHY_CTRL_BASE 0x0280 /* 3 - xMII */ #define PORT_SGMII_SEL BIT(7)