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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Michael Liang , Mohamed Khalfella , Yuanyuan Zhong , Shay Drory , "Tariq Toukan" Subject: [PATCH net V2 03/12] net/mlx5: offset comp irq index in name by one Date: Tue, 9 Apr 2024 22:08:11 +0300 Message-ID: <20240409190820.227554-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240409190820.227554-1-tariqt@nvidia.com> References: <20240409190820.227554-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6730:EE_|PH7PR12MB5656:EE_ X-MS-Office365-Filtering-Correlation-Id: c9dabc6f-4d4c-43ed-4e22-08dc58c89239 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: d1tmdRidYinaHO4Pgb015PK1OVOqz8oXf2waPIsWkb4EcncA1xjURroEKIus1b3vuBt27lKVp6KkGSaL+tiMSgvOLvIl8c3lHrPNYCDDZAeXjG9Aq8khFgMZ4D+R+1e/ZPcULG+EY6GG9UTIHpk8SGWP8AWzyQ+UVvKsT+p3U0NoAwHtUE/Mvg2ViJiRfNGYuIpE4tyo6annYkiIOApgXwBm4Wgaiqx/S6hTHtKphur9ETg0KlvmFU5CUQ8DFYyyWCvF1u2DHEQEc4+v5vtEUWe5MSQq8a0gtfhjsu/ScmTJppMJbCwJzq9qCktRlJwhYibk2w2tdlZy7N/vNQ6eei22W+gzuuojTHFLtyew6xcZZ62uvB5WD2vT6r2Sk8TWfGNJ2GE0Nh42hoiQu3BOH0TFhLUXhTuFn/d5rBU0D+N2Hs8qLwlN7V2T+VZk6RDp0ngbGoA2VgNlCQlzrHCSB8SiKH2h2nikTYyMT6rNTrU0jDlnEjRD75USjInxXCq65SRD7TT9vkbzBnuArHGIyXHD5FyThBjTnC0cbElybFbsw27t0Y30gUg6dXnnDta1PesDokSBa3UxP1e0ZkrlAb0dVEbiCxS8R976e+CZDupyNPrG1Tw6HqD9iiShbvPHIVjNjIjdeAjasy0BcrvGUxikK4Pp/GnatrNTmrC1FB894q0zSWcxMOrXT7mDaE7OZOg5LX0ljoiY7HpT6OOHehnHhgJHb2p07o1at5p7B4Olu1NysL718f38XwsNYWNr X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(82310400014)(36860700004)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2024 19:09:24.8137 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c9dabc6f-4d4c-43ed-4e22-08dc58c89239 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6730.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5656 X-Patchwork-Delegate: kuba@kernel.org From: Michael Liang The mlx5 comp irq name scheme is changed a little bit between commit 3663ad34bc70 ("net/mlx5: Shift control IRQ to the last index") and commit 3354822cde5a ("net/mlx5: Use dynamic msix vectors allocation"). The index in the comp irq name used to start from 0 but now it starts from 1. There is nothing critical here, but it's harmless to change back to the old behavior, a.k.a starting from 0. Fixes: 3354822cde5a ("net/mlx5: Use dynamic msix vectors allocation") Reviewed-by: Mohamed Khalfella Reviewed-by: Yuanyuan Zhong Signed-off-by: Michael Liang Reviewed-by: Shay Drory Signed-off-by: Saeed Mahameed Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c index 4dcf995cb1a2..6bac8ad70ba6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c @@ -19,6 +19,7 @@ #define MLX5_IRQ_CTRL_SF_MAX 8 /* min num of vectors for SFs to be enabled */ #define MLX5_IRQ_VEC_COMP_BASE_SF 2 +#define MLX5_IRQ_VEC_COMP_BASE 1 #define MLX5_EQ_SHARE_IRQ_MAX_COMP (8) #define MLX5_EQ_SHARE_IRQ_MAX_CTRL (UINT_MAX) @@ -246,6 +247,7 @@ static void irq_set_name(struct mlx5_irq_pool *pool, char *name, int vecidx) return; } + vecidx -= MLX5_IRQ_VEC_COMP_BASE; snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", vecidx); } @@ -585,7 +587,7 @@ struct mlx5_irq *mlx5_irq_request_vector(struct mlx5_core_dev *dev, u16 cpu, struct mlx5_irq_table *table = mlx5_irq_table_get(dev); struct mlx5_irq_pool *pool = table->pcif_pool; struct irq_affinity_desc af_desc; - int offset = 1; + int offset = MLX5_IRQ_VEC_COMP_BASE; if (!pool->xa_num_irqs.max) offset = 0;