@@ -27,6 +27,7 @@ config TEHUTI_TN40
tristate "Tehuti Networks TN40xx 10G Ethernet adapters"
depends on PCI
select FW_LOADER
+ select PHYLINK
help
This driver supports 10G Ethernet adapters using Tehuti Networks
TN40xx chips. Currently, adapters with Applied Micro Circuits
@@ -5,5 +5,5 @@
obj-$(CONFIG_TEHUTI) += tehuti.o
-tn40xx-y := tn40.o tn40_mdio.o
+tn40xx-y := tn40.o tn40_mdio.o tn40_phy.o
obj-$(CONFIG_TEHUTI_TN40) += tn40xx.o
@@ -7,6 +7,7 @@
#include <linux/if_vlan.h>
#include <linux/netdevice.h>
#include <linux/pci.h>
+#include <linux/phylink.h>
#include "tn40.h"
@@ -1187,21 +1188,25 @@ static void tn40_link_changed(struct tn40_priv *priv)
u32 link = tn40_read_reg(priv,
TN40_REG_MAC_LNK_STAT) & TN40_MAC_LINK_STAT;
if (!link) {
- if (netif_carrier_ok(priv->ndev) && priv->link)
+ if (netif_carrier_ok(priv->ndev) && priv->link) {
netif_stop_queue(priv->ndev);
+ phylink_mac_change(priv->phylink, false);
+ }
priv->link = 0;
if (priv->link_loop_cnt++ > TN40_LINK_LOOP_MAX) {
/* MAC reset */
tn40_set_link_speed(priv, 0);
+ tn40_set_link_speed(priv, priv->speed);
priv->link_loop_cnt = 0;
}
tn40_write_reg(priv, 0x5150, 1000000);
return;
}
- if (!netif_carrier_ok(priv->ndev) && !link)
+ if (!netif_carrier_ok(priv->ndev) && !link) {
netif_wake_queue(priv->ndev);
-
+ phylink_mac_change(priv->phylink, true);
+ }
priv->link = link;
}
@@ -1483,6 +1488,9 @@ static int tn40_close(struct net_device *ndev)
{
struct tn40_priv *priv = netdev_priv(ndev);
+ phylink_stop(priv->phylink);
+ phylink_disconnect_phy(priv->phylink);
+
napi_disable(&priv->napi);
netif_napi_del(&priv->napi);
tn40_disable_interrupts(priv);
@@ -1498,10 +1506,17 @@ static int tn40_open(struct net_device *dev)
struct tn40_priv *priv = netdev_priv(dev);
int ret;
+ ret = phylink_connect_phy(priv->phylink, priv->phydev);
+ if (ret)
+ return ret;
+
tn40_sw_reset(priv);
+ phylink_start(priv->phylink);
ret = tn40_start(priv);
if (ret) {
netdev_err(dev, "failed to start %d\n", ret);
+ phylink_stop(priv->phylink);
+ phylink_disconnect_phy(priv->phylink);
return ret;
}
napi_enable(&priv->napi);
@@ -1794,19 +1809,25 @@ static int tn40_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
TN40_IR_TMR1;
tn40_mac_init(priv);
-
+ ret = tn40_phy_register(priv);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to set up PHY.\n");
+ goto err_free_irq;
+ }
ret = tn40_priv_init(priv);
if (ret) {
dev_err(&pdev->dev, "failed to initialize tn40_priv.\n");
- goto err_free_irq;
+ goto err_unregister_phydev;
}
ret = register_netdev(ndev);
if (ret) {
dev_err(&pdev->dev, "failed to register netdev.\n");
- goto err_free_irq;
+ goto err_unregister_phydev;
}
return 0;
+err_unregister_phydev:
+ tn40_phy_unregister(priv);
err_free_irq:
pci_free_irq_vectors(pdev);
err_unset_drvdata:
@@ -1827,6 +1848,7 @@ static void tn40_remove(struct pci_dev *pdev)
unregister_netdev(ndev);
+ tn40_phy_unregister(priv);
pci_free_irq_vectors(priv->pdev);
pci_set_drvdata(pdev, NULL);
iounmap(priv->regs);
@@ -161,6 +161,10 @@ struct tn40_priv {
struct tn40_rx_page_table rx_page_table;
struct mii_bus *mdio;
+ struct phy_device *phydev;
+ struct phylink *phylink;
+ struct phylink_config phylink_config;
+ int speed;
};
/* RX FREE descriptor - 64bit */
@@ -242,4 +246,7 @@ static inline void tn40_write_reg(struct tn40_priv *priv, u32 reg, u32 val)
int tn40_mdiobus_init(struct tn40_priv *priv);
+int tn40_phy_register(struct tn40_priv *priv);
+void tn40_phy_unregister(struct tn40_priv *priv);
+
#endif /* _TN40XX_H */
new file mode 100644
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) Tehuti Networks Ltd. */
+
+#include <linux/netdevice.h>
+#include <linux/pci.h>
+#include <linux/phylink.h>
+
+#include "tn40.h"
+
+static void tn40_link_up(struct phylink_config *config, struct phy_device *phy,
+ unsigned int mode, phy_interface_t interface,
+ int speed, int duplex, bool tx_pause, bool rx_pause)
+{
+ struct tn40_priv *priv = container_of(config, struct tn40_priv,
+ phylink_config);
+
+ priv->speed = speed;
+}
+
+static void tn40_link_down(struct phylink_config *config, unsigned int mode,
+ phy_interface_t interface)
+{
+}
+
+static void tn40_mac_config(struct phylink_config *config, unsigned int mode,
+ const struct phylink_link_state *state)
+{
+}
+
+static const struct phylink_mac_ops tn40_mac_ops = {
+ .mac_config = tn40_mac_config,
+ .mac_link_up = tn40_link_up,
+ .mac_link_down = tn40_link_down,
+};
+
+int tn40_phy_register(struct tn40_priv *priv)
+{
+ struct phylink_config *config;
+ struct phy_device *phydev;
+ struct phylink *phylink;
+
+ phydev = phy_find_first(priv->mdio);
+ if (!phydev) {
+ dev_err(&priv->pdev->dev, "PHY isn't found\n");
+ return -1;
+ }
+
+ config = &priv->phylink_config;
+ config->dev = &priv->ndev->dev;
+ config->type = PHYLINK_NETDEV;
+ config->mac_capabilities = MAC_10000FD | MLO_AN_PHY;
+ __set_bit(PHY_INTERFACE_MODE_XAUI, config->supported_interfaces);
+
+ phylink = phylink_create(config, NULL, PHY_INTERFACE_MODE_XAUI,
+ &tn40_mac_ops);
+ if (IS_ERR(phylink))
+ return PTR_ERR(phylink);
+
+ priv->phydev = phydev;
+ priv->phylink = phylink;
+ return 0;
+}
+
+void tn40_phy_unregister(struct tn40_priv *priv)
+{
+ phylink_destroy(priv->phylink);
+}
This patch adds supports for multiple PHY hardware with PHYLIB. The adapters with TN40xx chips use multiple PHY hardware; AMCC QT2025, TI TLK10232, Aqrate AQR105, and Marvell 88X3120, 88X3310, and MV88E2010. For now, the PCI ID table of this driver enables adapters using only QT2025 PHY. I've tested this driver and the QT2025 PHY driver with Edimax EN-9320 10G adapter. Signed-off-by: FUJITA Tomonori <fujita.tomonori@gmail.com> --- drivers/net/ethernet/tehuti/Kconfig | 1 + drivers/net/ethernet/tehuti/Makefile | 2 +- drivers/net/ethernet/tehuti/tn40.c | 34 ++++++++++--- drivers/net/ethernet/tehuti/tn40.h | 7 +++ drivers/net/ethernet/tehuti/tn40_phy.c | 67 ++++++++++++++++++++++++++ 5 files changed, 104 insertions(+), 7 deletions(-) create mode 100644 drivers/net/ethernet/tehuti/tn40_phy.c