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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Shay Drory , Mark Bloch , Tariq Toukan Subject: [PATCH net-next 1/3] net/mlx5: Enable 8 ports LAG Date: Sun, 12 May 2024 15:43:03 +0300 Message-ID: <20240512124306.740898-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240512124306.740898-1-tariqt@nvidia.com> References: <20240512124306.740898-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B1:EE_|PH7PR12MB8428:EE_ X-MS-Office365-Filtering-Correlation-Id: dde0d0e5-a209-460f-b852-08dc72813a9d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|1800799015|376005|36860700004|82310400017; X-Microsoft-Antispam-Message-Info: F5OJ1Q4/EPKPs8XYWq5tLjeLZAWnz3eYnH60aH761BuVZ5cTiuaBQKMr//g4adjVeriT4IcaU4Z4K4TmKL40rG3qTO7y42YkIasmXg3WDO/cWFtzpGGG6IlpvHDDLuVgKldOZpKZgHN7l/HF155ktGZcphxe1/J1EqmNyyliEByWEaXsK/gsQ3KHPtqJUNtrtbJgnachl0Y88LPEP2YNfH5FZ9A07Rsu6fZCo0yfkeZ+2qI5M9OaqW40ZOVFm1NdB8+r6lNwIXu5IBvegIV9AeLhTmMpN/REBBf+IOaU/XWpAQBh1caY0SIxQ59o6QSF4EvOj+gJFzVG+CDtMucIQaCM4jRaFRA+TE2KP2RLkZ9mRYE+ChbKkUz2ewXbh1wJ3dPAH+8YD2cS096wAWbrN/l6gVwkpbSgv79HpJBXUlqg1BMwiEYvUu9hQpHpz0k9bX8hlTdrdNEHYsTjZhGNtTcu2n/QVcTNpoCIsmCqfaK+VxvJaJdqbnd/ZHqRw+zG5lpNyDPlxheenQLLyUhZ5Jcp8Y3ffzzlzHhpHpkF7R3Ey+YE+VhgeeRRJ9ej0upLrzR4wzkQSnpom84VHi4X3g+2sqGWWKKF7f495bkA3BPwWUMEbWP5goCuv2NsrOAjauE1yRoOryBPksu82yKtRbuWIsbm9mA6VF4VZvU7gddl7DLJEoQvZur3fTcDx8qF/eEP/m40IT7NJ9wB5TOiQ2EQ3gJpC9nTGib1641PN+wI71jm+RIqamfO6narUNM9YLebBL4gzQZHUoCv4c8QudMjHmRWDh3C7nbxCNDt45D+9k+JwTnj6oqZwe6nB6Bm39ExXsnIT7I0O3vdaVUjgu+ehXcWg/0IylYwJJEypxY0Z0f2kEJ0RQ/btvDNfBmaZj0byt86rmmUzEIcHXHNzHjz8ThaRNKydgnahcyLkVGbqIUk0JahYv9WLaus9PU/7m8ntQBVKuBHyiP1gY5W2c4sU+gwinXeHxbW3I186tXkYGA8F0GvQA47VpVR8mt+IDkuqs47fzo863iCWYk1S40Vuywo3DxLrAvjVFUvi9fe1YU82+5YajRRs8rHsEeNngEYCvf80MiSm1UNPVHnqnmjH9wuvhTiTEzR1rhkOM0YgRgqAUcHEiExV7to5BrVXuclCR4gNLBpCa3fGD0XogQ6HpEHvhNDuesWOR1CJKd/JMb+/gaDRtrAijeqzmSHPQCPUtGaGaWaPg4UFPvbNbdVEAp1xAWbGjhlgNBJ9xMY+EU/VEEvQC0QvXr8rT2HuQo096Rd/n1VZSK5zB8aiwc2CVVKfjvczKz+7hnYmIOQ/IOPAGGZqIHb8v5coo80NUdWBz20OvcvK4UI2Q6UTyRv8/s2dRi6vPyD+/GHv+k= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(376005)(36860700004)(82310400017);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2024 12:44:13.7967 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dde0d0e5-a209-460f-b852-08dc72813a9d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8428 X-Patchwork-Delegate: kuba@kernel.org From: Shay Drory This patch adds to mlx5 drivers support for 8 ports HCAs. Starting with ConnectX-8 HCAs with 8 ports are possible. As most driver parts aren't affected by such configuration most driver code is unchanged. Specially the only affected areas are: - Lag - Multiport E-Switch - Single FDB E-Switch All of the above are already factored in generic way, and LAG and VF LAG are tested, so all that left is to change a #define and remove checks which are no longer needed. However, Multiport E-Switch is not tested yet, so it is left untouched. This patch will allow to create hardware LAG/VF LAG when all 8 ports are added to the same bond device. for example, In order to activate the hardware lag a user can execute the following: ip link add bond0 type bond ip link set bond0 type bond miimon 100 mode 2 ip link set eth2 master bond0 ip link set eth3 master bond0 ip link set eth4 master bond0 ip link set eth5 master bond0 ip link set eth6 master bond0 ip link set eth7 master bond0 ip link set eth8 master bond0 ip link set eth9 master bond0 Where eth2, eth3, eth4, eth5, eth6, eth7, eth8 and eth9 are the PFs of the same HCA. Signed-off-by: Shay Drory Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c | 3 --- include/linux/mlx5/driver.h | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c index 69d482f7c5a2..5e2171ff0a89 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -713,7 +713,6 @@ int mlx5_deactivate_lag(struct mlx5_lag *ldev) return 0; } -#define MLX5_LAG_OFFLOADS_SUPPORTED_PORTS 4 bool mlx5_lag_check_prereq(struct mlx5_lag *ldev) { #ifdef CONFIG_MLX5_ESWITCH @@ -739,8 +738,6 @@ bool mlx5_lag_check_prereq(struct mlx5_lag *ldev) if (mlx5_eswitch_mode(ldev->pf[i].dev) != mode) return false; - if (mode == MLX5_ESWITCH_OFFLOADS && ldev->ports > MLX5_LAG_OFFLOADS_SUPPORTED_PORTS) - return false; #else for (i = 0; i < ldev->ports; i++) if (mlx5_sriov_is_enabled(ldev->pf[i].dev)) diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index bf9324a31ae9..8218588688b5 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -85,7 +85,7 @@ enum mlx5_sqp_t { }; enum { - MLX5_MAX_PORTS = 4, + MLX5_MAX_PORTS = 8, }; enum {