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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin Cc: Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH RFC net-next 1/3] net: stmmac: Prevent RGSMIIIS IRQs flood Date: Sat, 25 May 2024 00:02:57 +0300 Message-ID: <20240524210304.9164-1-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Without reading the GMAC_RGSMIIIS/MAC_PHYIF_Control_Status the IRQ line won't be de-asserted causing interrupt handler executed over and over. As a quick-fix let's just dummy-read the CSR for now. Signed-off-by: Serge Semin --- drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c | 2 ++ drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c index adb872d5719f..2ae8467c588e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c @@ -304,6 +304,8 @@ static int dwmac1000_irq_status(struct mac_device_info *hw, dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x); if (intr_status & PCS_RGSMIIIS_IRQ) { + /* TODO Dummy-read to clear the IRQ status */ + readl(ioaddr + GMAC_RGSMIIIS); phylink_pcs_change(&hw->mac_pcs, false); x->irq_rgmii_n++; } diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c index a892d361a4e4..cd2ca1d0222c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c @@ -896,6 +896,8 @@ static int dwmac4_irq_status(struct mac_device_info *hw, dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x); if (intr_status & PCS_RGSMIIIS_IRQ) { + /* TODO Dummy-read to clear the IRQ status */ + readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS); phylink_pcs_change(&hw->mac_pcs, false); x->irq_rgmii_n++; }