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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Rahul Rameshbabu , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next 6/6] net/mlx5e: Support SWP-mode offload L4 csum calculation Date: Fri, 14 Jun 2024 00:00:36 +0300 Message-ID: <20240613210036.1125203-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240613210036.1125203-1-tariqt@nvidia.com> References: <20240613210036.1125203-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9DA:EE_|CH2PR12MB4118:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c22c787-4eda-4f5f-f02f-08dc8bec1f66 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230035|376009|82310400021|1800799019|36860700008; X-Microsoft-Antispam-Message-Info: i+SS5Ai6ilHZ+KMD0q7uGcXD2ZxRYFCIX0IukeCJkDYJDFZaUj36rN3Nvoemh35P7JiP+YUCZ0d0u1vgKwjbzT1q+MopIy+Bu4lB1Lbe3U1/VBNII8IZeGcIBnnEOTlX9KIwS9XpWl5e7yQlPecqMbnxmxvtsptDXSVMyMLk/NlG3JpSopIaahNArFOkjz4ZUbjJGXCFlv8KL08n/cG/kMTUtgp+A8LX4xiwBgBjFmks9LUiW67JvUalj62zSmnh6V7D0z+WYDzOrgagYmCMjd51Bie78Xyq93olMmx1UgAkOjzAV8tBbCoFc66eXdQhfdlO+i2TdxxXYJrsJ84l2/U5JOTcV4LENu8MJVCTa9/7gKJn/m6/c9kTi7CPJDT2nsFEdh3VEJSP2JftxvT6XzIueBmIiUdUA7Rr0vZM3CRKT4kMBSCKGwAf03AU4PM0BWXbrHvkBVVScMfbCToq4dmKxmnfDp5svj6YkPF62Ocxnn6ROxknCOEojqr40xEZ/z9rP6X4QRfb1qvjGS4ELDpxyfnKIWRPwoS1NV3etC7DnSYgX2MhuHhOz0k4tLi7Kg9vO4clvziF2LpgxPGj4OHK+920zzHpf5f1ikDOhlD/l2vBQrHtrFcJSqH+qYZPE6ArSZmamLZa4jYEZqRLRm/0pLsjOvkkcHiZVGE6ekajePdseQo07E+aTevSsujFD/knS9DNs45+Bgloz7Q2G2Ftep9qCUtbNs77JTBa5acifSWtoh5XLzmm0gCnQpthHDfAfWq7GyYHt+fFkxGzyGoP0cLRITica5W3WoWrUobgoh/wOqIPlfBx0bAolVfea/kq/tEHnikjhWoP4tzbEFeBG9gwHXDqjkNBjmICJqTb0fc7863IryucZv0xLbIrubbOZmmSEUDm/HmlphlGZFZR7RjolAEizmb7gDYBExBHSyV1XUny3RNnQQWqjqPVAd2YjYoGvNhgtqHYW8CgpsaEVzVzTEeD5pKUl5j7puaVxm73Lo89unLTdOEYCBo6v6fCtwc1vxVPuiW+dce8GWYbaS8S3HhPrRRgVFu65rQu9hY0GAj3YB8MDftfSEeHDm87FyrreWX/o02CBEGtmgr2Z4Apjz9ykGR76RroTMCXs3wopyinw7eidrCOkQjr9GwlZFLh5S5GxmuBsWnBhJddLghu0hDirvndwng0uqWToGJPjRuSrlGyP2+ftIOiHB7BZkqgFhMdH+UNOHo2JclKIKc0S3EpXXXB/eB5JJkMTmerRuDhm3eQUorRYZKBJ2XweguFGNuipvaokCXkOT23h1LWi5FVxZtT4Vbi9FgkfYt8izIwIjggucoeaJhoPibulYGFuOv8Ito6hG9heT4HfzQ6+j5tF66GcZ+HGVQe12RzZk6ueK7+mw+SBJiHF+v//Q5trkD4Ld6tJLi4Yg== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230035)(376009)(82310400021)(1800799019)(36860700008);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2024 21:02:23.4056 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c22c787-4eda-4f5f-f02f-08dc8bec1f66 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9DA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4118 X-Patchwork-Delegate: kuba@kernel.org From: Rahul Rameshbabu Calculate the pseudo-header checksum for both IPSec transport mode and IPSec tunnel mode for mlx5 devices that do not implement a pure hardware checksum offload for L4 checksum calculation. Introduce a capability bit that identifies such mlx5 devices. Signed-off-by: Rahul Rameshbabu Reviewed-by: Gal Pressman Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/en/txrx.h | 37 +++++++++++++++++++ .../mellanox/mlx5/core/en_accel/ipsec_rxtx.h | 6 ++- include/linux/mlx5/mlx5_ifc.h | 3 +- 3 files changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h index d1f0f868d494..5ec468268d1a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h @@ -6,6 +6,8 @@ #include "en.h" #include +#include +#include #define MLX5E_TX_WQE_EMPTY_DS_COUNT (sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) @@ -479,6 +481,41 @@ mlx5e_set_eseg_swp(struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg, } } +static inline void +mlx5e_swp_encap_csum_partial(struct mlx5_core_dev *mdev, struct sk_buff *skb, bool tunnel) +{ + const struct iphdr *ip = tunnel ? inner_ip_hdr(skb) : ip_hdr(skb); + const struct ipv6hdr *ip6; + struct tcphdr *th; + struct udphdr *uh; + int len; + + if (!MLX5_CAP_ETH(mdev, swp_csum_l4_partial) || !skb_is_gso(skb)) + return; + + if (skb_is_gso_tcp(skb)) { + th = inner_tcp_hdr(skb); + len = skb_shinfo(skb)->gso_size + inner_tcp_hdrlen(skb); + + if (ip->version == 4) { + th->check = ~tcp_v4_check(len, ip->saddr, ip->daddr, 0); + } else { + ip6 = tunnel ? inner_ipv6_hdr(skb) : ipv6_hdr(skb); + th->check = ~tcp_v6_check(len, &ip6->saddr, &ip6->daddr, 0); + } + } else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { + uh = (struct udphdr *)skb_inner_transport_header(skb); + len = skb_shinfo(skb)->gso_size + sizeof(struct udphdr); + + if (ip->version == 4) { + uh->check = ~udp_v4_check(len, ip->saddr, ip->daddr, 0); + } else { + ip6 = tunnel ? inner_ipv6_hdr(skb) : ipv6_hdr(skb); + uh->check = ~udp_v6_check(len, &ip6->saddr, &ip6->daddr, 0); + } + } +} + #define MLX5E_STOP_ROOM(wqebbs) ((wqebbs) * 2 - 1) static inline u16 mlx5e_stop_room_for_wqe(struct mlx5_core_dev *mdev, u16 wqe_size) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h index 359050f0b54d..3cc640669247 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.h @@ -116,6 +116,7 @@ static inline bool mlx5e_ipsec_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb, struct mlx5_wqe_eth_seg *eseg) { + struct mlx5_core_dev *mdev = sq->mdev; u8 inner_ipproto; if (!mlx5e_ipsec_eseg_meta(eseg)) @@ -125,9 +126,12 @@ mlx5e_ipsec_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb, inner_ipproto = xfrm_offload(skb)->inner_ipproto; if (inner_ipproto) { eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM; - if (inner_ipproto == IPPROTO_TCP || inner_ipproto == IPPROTO_UDP) + if (inner_ipproto == IPPROTO_TCP || inner_ipproto == IPPROTO_UDP) { + mlx5e_swp_encap_csum_partial(mdev, skb, true); eseg->cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM; + } } else if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { + mlx5e_swp_encap_csum_partial(mdev, skb, false); eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM; sq->stats->csum_partial_inner++; } diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 466dcda40bb5..66b921c81c0f 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1093,7 +1093,8 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits { u8 tunnel_stateless_ip_over_ip_tx[0x1]; u8 reserved_at_2e[0x2]; u8 max_vxlan_udp_ports[0x8]; - u8 reserved_at_38[0x6]; + u8 swp_csum_l4_partial[0x1]; + u8 reserved_at_39[0x5]; u8 max_geneve_opt_len[0x1]; u8 tunnel_stateless_geneve_rx[0x1];