From patchwork Fri Jun 21 12:20:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2t5TGFrZSBIdWFuZyAo6buD5ZWf5r6kKQ==?= X-Patchwork-Id: 13707487 X-Patchwork-Delegate: kuba@kernel.org Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CD4913777F; Fri, 21 Jun 2024 12:22:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718972528; cv=none; b=WW9mCI3/M1C16DrGB/wPiS1X51TXkaCuL/Y+0tPgMda14heBSDIoKqjgTQna7Y2YYjQ0gFc9A/spF6sm8CVQeAwSDQeGpNBTS1wA5hVfNcMLjOipGpTpqb163v62N+ilMTD54e97QFy9uJllQqvtjDn3qyw/Sv8xE7efCsH23uY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718972528; c=relaxed/simple; bh=mfpaJtnoVAcQNpvHr7zMKF5zSWfzTgSiU09srOc3Ho4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o4hC0i9UpDNLxIVOiEOvSgXksvjlDqnzj3Hs7UcL/cGlaCzqohZ+SHfi9gG30A75Rrv/7JOYi01UnDFxLD6qQYVf34PU4qyN5O8dEAcrPbuCX5HVh6Ioe04JB+RaPzY1+fARCtke4N5STWxbpYYKNCg9oJPF+NkVwyqPpkck1Ok= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=D1/pLC5I; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="D1/pLC5I" X-UUID: db62f5ba2fc811ef99dc3f8fac2c3230-20240621 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ho6xCrD2lSX/taMibZlSm4+S+GOP9pQr5GcmafIlMGw=; b=D1/pLC5I2XL+Kx+gurBjUfW+wJ9Uhj3hex9JUkWMb/br5IOyTwbesHVHMjrM0HmuEC5EmtkpQzPwm6G9qoFKI7yTMy/6OPkfXAR18F+HejsouK/xBO7LP5nqleQKpdkUjiv+zjbEJfs1EEf1MWghK7hXbkef9rcGJRysubcBf74=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.39,REQID:93764d42-d2c6-4a1a-a650-585b5f6ed72e,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:393d96e,CLOUDID:cd27dd44-4544-4d06-b2b2-d7e12813c598,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: db62f5ba2fc811ef99dc3f8fac2c3230-20240621 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 475768820; Fri, 21 Jun 2024 20:21:59 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 21 Jun 2024 20:21:57 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 21 Jun 2024 20:21:58 +0800 From: Sky Huang To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , , , , CC: Steven Liu , SkyLake.Huang Subject: [PATCH net-next v8 02/13] net: phy: mediatek: Fix spelling errors and rearrange variables Date: Fri, 21 Jun 2024 20:20:34 +0800 Message-ID: <20240621122045.30732-3-SkyLake.Huang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240621122045.30732-1-SkyLake.Huang@mediatek.com> References: <20240621122045.30732-1-SkyLake.Huang@mediatek.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N X-Patchwork-Delegate: kuba@kernel.org From: "SkyLake.Huang" This patch fixes spelling errors which comes from mediatek-ge-soc.c and rearrange variables with reverse Xmas tree order. Signed-off-by: SkyLake.Huang Reviewed-by: Andrew Lunn --- drivers/net/phy/mediatek/mtk-ge-soc.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediatek/mtk-ge-soc.c index f4f9412..0eb5395 100644 --- a/drivers/net/phy/mediatek/mtk-ge-soc.c +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c @@ -408,16 +408,17 @@ static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) { - int i; - int bias[16] = {}; - const int vals_9461[16] = { 7, 1, 4, 7, - 7, 1, 4, 7, - 7, 1, 4, 7, - 7, 1, 4, 7 }; const int vals_9481[16] = { 10, 6, 6, 10, 10, 6, 6, 10, 10, 6, 6, 10, 10, 6, 6, 10 }; + const int vals_9461[16] = { 7, 1, 4, 7, + 7, 1, 4, 7, + 7, 1, 4, 7, + 7, 1, 4, 7 }; + int bias[16] = {}; + int i; + switch (phydev->drv->phy_id) { case MTK_GPHY_ID_MT7981: /* We add some calibration to efuse values @@ -1069,10 +1070,10 @@ static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, static int mt798x_phy_calibration(struct phy_device *phydev) { + struct nvmem_cell *cell; int ret = 0; - u32 *buf; size_t len; - struct nvmem_cell *cell; + u32 *buf; cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); if (IS_ERR(cell)) { @@ -1415,7 +1416,7 @@ static int mt7988_phy_probe_shared(struct phy_device *phydev) * LED_C and LED_D respectively. At the same time those pins are used to * bootstrap configuration of the reference clock source (LED_A), * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). - * In practise this is done using a LED and a resistor pulling the pin + * In practice this is done using a LED and a resistor pulling the pin * either to GND or to VIO. * The detected value at boot time is accessible at run-time using the * TPBANK0 register located in the gpio base of the pinctrl, in order