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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Daniel Jurgens , Parav Pandit , William Tu , Tariq Toukan Subject: [PATCH net 1/7] net/mlx5: IFC updates for changing max EQs Date: Mon, 24 Jun 2024 10:29:55 +0300 Message-ID: <20240624073001.1204974-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240624073001.1204974-1-tariqt@nvidia.com> References: <20240624073001.1204974-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E6:EE_|DM4PR12MB5985:EE_ X-MS-Office365-Filtering-Correlation-Id: 82fbb8bd-af90-4fe8-cb48-08dc941fa6aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|36860700010|376011|82310400023|1800799021; X-Microsoft-Antispam-Message-Info: Z5Wz656WGyoBFAzajnmaDB1Vh/oBKeARTXx7OdGlE1eDNZbu/QGU14gyCHIPDj6j0yq6EMgJKaLjxu3UP5jJkpAv0rmauHnengDVQAC2hBCWpYEIowDeURmwUhq5Ro/JzcPTV2924db+C6jHceaptfYGwoWCv4vx7z4h876d/T9gpErvQ67cwgMnVDtAClPPp98/udpTnBbPNfYFgsLFS3xFHWEdfqc3FrQl8cJkhsjJfXTfapU1io0BDo/sb6z+9Tlex4jXuJYkPDXmHzXorlqxQNsI1NmnIqREwVdkfyxlczKDHTQvH3ZQfAU6qj8FcTPvGsg4fhKvqRtS/Xcukh16AFg9RqttVW38mRlEQo1l+JGUWHUohfv5MqNKVg3pmr/oUOA4l2ERVJr1NVPs5eizUGZOiRHfShISyHHlJOtv/PEJUp3G8y929aUW+GeOW6SuGu0cFYwKvaVcU0h8bZ3GhpSEnGWVniBcpFbS5xrrH6Ei81LhK5Y/uF+AC8v7JnGT1/ee8/Ly/KjhiDDJYIlCJSVgNB4afp5bIOEdvc2TOzAYhHtotKR5+Z7U7HK/W/zdLHZS/1gud3LDlK8E0rbguoACVqLl4DWfTaRwlLqLaTCNEU0VXGK+ZerQfbqvzc4lZYBu9mfrosRHtfn3FFWnJ7fOWOwUMwywoc0jc65QVMnAs7qjPjU39/w+AqhjwL9e94NE6YrdjWQbiNOmhkn65rBXn5TqrRWdCIBeYqDfPXn2ig9AYRz3kThZjKanDSyC2PN6+r0kgdBli2yWnhHSOppvWisCJxPeiwFLdNx3bEFPySOrZnyXJXMtU2OVCEBGvefSDz7mqyYzxlbFsERKTtsSVJYNaQ98Jq+MyTupQU2Y9o2A19npIekOSiZpW8ywRraRmGOM0f81VL1Aqcpm4QmEUan5YNh2a9kCcvAlwyd8K6Vc2XsDbDRn3BV4AE5N4Jj/GEKgxgEJYOFU/mEZYiRNKuvji/Lly8vf61lQlynrvm9VW/j/ujsa9WbC1T0xCXfTKN1E+epO+G4HcXFfPeXGRg0VrtYZZ7RPLd6OJQ8zsxywOZTBNFL+Vv5o9G7QyjS6jS5tjXphl1FinaEOA4QlYOMgz5yRcRM+6lEq3xuxa3UGf5E2E54yQgfJMS7RmYv3JWdbYz2ZXyLGuv8PH62Hd6vuqgogvkgxEm6KYWUeZj44lkhlG7eS0+uFvUHNmkIxyn/EHlsV+j1r747E7C3ip2kAU1ZRdnS4d21txVb1ER2+O/R4wY9t9rAj03I26JxDCPHDYiJpSWYaIT12pw+nO7aWbDM8sOaesQ5VSTO3cVTTBC9xqgVv5863Dn9JFfV6UvGe0GIRz5vfJDgXtc8Ep0fPLAqLjLiYdTAOBDMHT4Xw2ItD15Lorq+XaJi+h1vq8a4Y1CCEV61EzQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230037)(36860700010)(376011)(82310400023)(1800799021);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 07:31:23.9938 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 82fbb8bd-af90-4fe8-cb48-08dc941fa6aa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5985 X-Patchwork-Delegate: kuba@kernel.org From: Daniel Jurgens Expose new capability to support changing the number of EQs available to other functions. Fixes: 93197c7c509d ("mlx5/core: Support max_io_eqs for a function") Signed-off-by: Daniel Jurgens Reviewed-by: Parav Pandit Reviewed-by: William Tu Signed-off-by: Tariq Toukan --- include/linux/mlx5/mlx5_ifc.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 5df52e15f7d6..d45bfb7cf81d 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -2029,7 +2029,11 @@ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 pcc_ifa2[0x1]; u8 reserved_at_3f1[0xf]; - u8 reserved_at_400[0x400]; + u8 reserved_at_400[0x40]; + + u8 reserved_at_440[0x8]; + u8 max_num_eqs_24b[0x18]; + u8 reserved_at_460[0x3a0]; }; enum mlx5_ifc_flow_destination_type {