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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Daniel Jurgens , Parav Pandit , William Tu , Tariq Toukan Subject: [PATCH net 2/7] net/mlx5: Use max_num_eqs_24b capability if set Date: Mon, 24 Jun 2024 10:29:56 +0300 Message-ID: <20240624073001.1204974-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240624073001.1204974-1-tariqt@nvidia.com> References: <20240624073001.1204974-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E5:EE_|DS7PR12MB5742:EE_ X-MS-Office365-Filtering-Correlation-Id: a5df0691-71aa-40a5-990d-08dc941fa858 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|376011|1800799021|82310400023|36860700010; X-Microsoft-Antispam-Message-Info: 72Zr9i4pjeAd8M9TI8jy0wps6g4EiCIV5SySNBAjyUGOWWjqQS4nrhmdbyYGODyPUCRHsHg2NJtp5V78gzVn+4Jlr+F8AOSEaiaqUssaDMzfWCoJLkWE7ZdBTveDvSroRqDMKdeqKVmtiwSmybOsOCjv1qc4HTNIQ/mj0hpA7Q96TkYAJMxuqcKDYpuhZP2G1lLgcJPqADy4W+n2UHOVwtz7UCPPlOQBafJf1hvRbe5UQT1rxSVEwmyAkv81TuM9BlbrJ5EAZmcCqLZjZbJUBn2uZUqTBSDoFPmQZKy5EtiaRx+NBZv9NuuGghwrI8b8hd2EDRmUCiik8XuFTYK0Mv33uWTrOZwQVW+NLlVkJUhlw5RgM+8LTgcc0Q5ECpW7G9qkXU7q1NBen7+skxMXWbzX0Od8Sd3WIa7U9ga/5qZDK7cEmr0ULUcxVoavPD8OL46hfwxlHXFq6wmX5RosfrDQRKOccfXKwQ95FlBvT0Ev3aA0C2FJnEtvBBNKo6PyyTbSz7KRQ/IYez9hFvs/JS6ESg74wC17AXmvzh0j0mOoyWLdPp6/6x2TH6EvAwXwTRcguvGuT/UWYzreO7VEeRhqjIRJdar7xFDweYSSgfR3uC0/og6S4aGf1l9W2mpOqw/Jjj+T1CPzHwBF2/Ey8JUoXpIHlu6sn82cZcBywBnQiNptzOBGf2RA4d/mRVZBvohSp4rpYLtqxQJvRnS/rgByUSJq1euwaYlp0724NdfcsuOlA6Wk91UwBqk6dwTe6t+hIUlp5hFdJXtaT69u2U4ZNAc2mVPYIrQoNmowkWv5m/qlmj/MiG2R7S7xkSG7wpoXTUyydCLb/S4StM90q0+sDukI6R+hWn4uT0YJkZkbxrash7gdGphNGIHRODiT/NT9OpQ2ud8DzkpXHIj4jTLfTyOdfzJpObtBrK6QPqiA5rav+nypqhcJqRwhq2A8nIxF/2VhF30y79RwN5orvtP6aW6/2ZVmMSWScuDMtiPms04OdM1lE4YJ9V3m903ftzo67glYhrIOUAmNAF1K+PjLaqD5wfGyyULTOLDmNKPTm4tEciLm6tlVVtJxB8nmEPMYOH0USyI2o67rIWjbIe4j0gHO3ngQWlyQAoiB4n1mqABZNrve6NM8Y/rDQedCVZtZTpLrL3Z2q+Uy0aUjSd0YIjZHH7MNESFNZmdr8Mum9ZKsiFIXWqz2thaIKJKNQfBVUpLgaSbZfHIWiIg1oBo+BDzLavb/X7rBvxItzqJiBaob8HvGiTogXXNeiB9AAVXZrP4xiwlpKC+6Lf1wOIResPBm/OKK8ouWn0BQ+llv8rLGyDNlSmNceveBVswBmPXzo+bs15iJK0ezCfE1bKsnAqOjPOcFCm6d74hoGpD12nrq2KZc2lLxCVIlzXBo4H94xecf1mh7gX8XhSleoQ== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230037)(376011)(1800799021)(82310400023)(36860700010);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 07:31:26.8262 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a5df0691-71aa-40a5-990d-08dc941fa858 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5742 X-Patchwork-Delegate: kuba@kernel.org From: Daniel Jurgens A new capability with more bits is added. If it's set use that value as the maximum number of EQs available. This cap is also writable by the vhca_resource_manager to allow limiting the number of EQs available to SFs and VFs. Fixes: 93197c7c509d ("mlx5/core: Support max_io_eqs for a function") Signed-off-by: Daniel Jurgens Reviewed-by: Parav Pandit Reviewed-by: William Tu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/eq.c | 4 +--- drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h | 10 ++++++++++ drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c | 4 +--- 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c index 5693986ae656..ac1565c0c8af 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c @@ -1197,9 +1197,7 @@ static int get_num_eqs(struct mlx5_core_dev *dev) if (!mlx5_core_is_eth_enabled(dev) && mlx5_eth_supported(dev)) return 1; - max_dev_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ? - MLX5_CAP_GEN(dev, max_num_eqs) : - 1 << MLX5_CAP_GEN(dev, log_max_eq); + max_dev_eqs = mlx5_max_eq_cap_get(dev); num_eqs = min_t(int, mlx5_irq_table_get_num_comp(eq_table->irq_table), max_dev_eqs - MLX5_MAX_ASYNC_EQS); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h index c38342b9f320..a7fd18888b6e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -383,4 +383,14 @@ static inline int mlx5_vport_to_func_id(const struct mlx5_core_dev *dev, u16 vpo : vport; } +static inline int mlx5_max_eq_cap_get(const struct mlx5_core_dev *dev) +{ + if (MLX5_CAP_GEN_2(dev, max_num_eqs_24b)) + return MLX5_CAP_GEN_2(dev, max_num_eqs_24b); + + if (MLX5_CAP_GEN(dev, max_num_eqs)) + return MLX5_CAP_GEN(dev, max_num_eqs); + + return 1 << MLX5_CAP_GEN(dev, log_max_eq); +} #endif /* __MLX5_CORE_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c index fb8787e30d3f..401d39069680 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c @@ -711,9 +711,7 @@ int mlx5_irq_table_get_num_comp(struct mlx5_irq_table *table) int mlx5_irq_table_create(struct mlx5_core_dev *dev) { - int num_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ? - MLX5_CAP_GEN(dev, max_num_eqs) : - 1 << MLX5_CAP_GEN(dev, log_max_eq); + int num_eqs = mlx5_max_eq_cap_get(dev); int total_vec; int pcif_vec; int req_vec;