diff mbox series

[net,V2,1/7] net/mlx5: IFC updates for changing max EQs

Message ID 20240627180240.1224975-2-tariqt@nvidia.com (mailing list archive)
State Accepted
Commit 048a403648fcef8bd9f4f1a290c57b626ad16296
Delegated to: Netdev Maintainers
Headers show
Series mlx5 fixes 2024-06-27 | expand

Checks

Context Check Description
netdev/series_format success Posting correctly formatted
netdev/tree_selection success Clearly marked for net
netdev/ynl success Generated files up to date; no warnings/errors; no diff in generated;
netdev/fixes_present success Fixes tag present in non-next series
netdev/header_inline success No static functions without inline keyword in header files
netdev/build_32bit success Errors and warnings before: 859 this patch: 859
netdev/build_tools success Errors and warnings before: 0 this patch: 0
netdev/cc_maintainers fail 2 blamed authors not CCed: shayd@nvidia.com jiri@resnulli.us; 3 maintainers not CCed: shayd@nvidia.com jiri@resnulli.us linux-rdma@vger.kernel.org
netdev/build_clang success Errors and warnings before: 863 this patch: 863
netdev/verify_signedoff success Signed-off-by tag matches author and committer
netdev/deprecated_api success None detected
netdev/check_selftest success No net selftest shell script
netdev/verify_fixes success Fixes tag looks correct
netdev/build_allmodconfig_warn success Errors and warnings before: 866 this patch: 866
netdev/checkpatch success total: 0 errors, 0 warnings, 0 checks, 12 lines checked
netdev/build_clang_rust success No Rust files in patch. Skipping build
netdev/kdoc success Errors and warnings before: 0 this patch: 0
netdev/source_inline success Was 0 now: 0

Commit Message

Tariq Toukan June 27, 2024, 6:02 p.m. UTC 
From: Daniel Jurgens <danielj@nvidia.com>

Expose new capability to support changing the number of EQs available
to other functions.

Fixes: 93197c7c509d ("mlx5/core: Support max_io_eqs for a function")
Signed-off-by: Daniel Jurgens <danielj@nvidia.com>
Reviewed-by: Parav Pandit <parav@nvidia.com>
Reviewed-by: William Tu <witu@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
---
 include/linux/mlx5/mlx5_ifc.h | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

Comments

Tariq Toukan June 30, 2024, 7:30 a.m. UTC | #1 
On 27/06/2024 21:02, Tariq Toukan wrote:
> From: Daniel Jurgens <danielj@nvidia.com>
> 
> Expose new capability to support changing the number of EQs available
> to other functions.
> 
> Fixes: 93197c7c509d ("mlx5/core: Support max_io_eqs for a function")
> Signed-off-by: Daniel Jurgens <danielj@nvidia.com>
> Reviewed-by: Parav Pandit <parav@nvidia.com>
> Reviewed-by: William Tu <witu@nvidia.com>
> Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
> ---
>   include/linux/mlx5/mlx5_ifc.h | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
> index 5df52e15f7d6..d45bfb7cf81d 100644
> --- a/include/linux/mlx5/mlx5_ifc.h
> +++ b/include/linux/mlx5/mlx5_ifc.h
> @@ -2029,7 +2029,11 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {
>   	u8	   pcc_ifa2[0x1];
>   	u8	   reserved_at_3f1[0xf];
>   
> -	u8	   reserved_at_400[0x400];
> +	u8	   reserved_at_400[0x40];
> +
> +	u8	   reserved_at_440[0x8];
> +	u8	   max_num_eqs_24b[0x18];
> +	u8	   reserved_at_460[0x3a0];
>   };
>   
>   enum mlx5_ifc_flow_destination_type {

Hi,

Please note that this is expected to conflict with net-next commit:
99be56171fa9 net/mlx5e: SHAMPO, Re-enable HW-GRO.

Resolution is

         u8         reserved_at_400[0x1];
         u8         min_mkey_log_entity_size_fixed_buffer_valid[0x1];
         u8         reserved_at_402[0x1e];

         u8         reserved_at_420[0x20];

         u8         reserved_at_440[0x8];
         u8         max_num_eqs_24b[0x18];
         u8         reserved_at_460[0x3a0];

Thanks,
Tariq
diff mbox series

Patch

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 5df52e15f7d6..d45bfb7cf81d 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -2029,7 +2029,11 @@  struct mlx5_ifc_cmd_hca_cap_2_bits {
 	u8	   pcc_ifa2[0x1];
 	u8	   reserved_at_3f1[0xf];
 
-	u8	   reserved_at_400[0x400];
+	u8	   reserved_at_400[0x40];
+
+	u8	   reserved_at_440[0x8];
+	u8	   max_num_eqs_24b[0x18];
+	u8	   reserved_at_460[0x3a0];
 };
 
 enum mlx5_ifc_flow_destination_type {