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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Daniel Jurgens , Parav Pandit , William Tu , Tariq Toukan Subject: [PATCH net V2 2/7] net/mlx5: Use max_num_eqs_24b capability if set Date: Thu, 27 Jun 2024 21:02:35 +0300 Message-ID: <20240627180240.1224975-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240627180240.1224975-1-tariqt@nvidia.com> References: <20240627180240.1224975-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6A:EE_|DM4PR12MB6301:EE_ X-MS-Office365-Filtering-Correlation-Id: 76a0ad8e-ab59-47e6-6bd2-08dc96d3907b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: NLrSiHe7Wp1DEYY+7S50lDfISn++MGYKHg2udVHwSIjxCi4re/umUFyZwHBvB0929wYpjcQsNoe1kk8llRfbFi2CQlgO/TnyxJxfdvRk5ubqCML/cg4X6BkxmIpIL6bp7QaOdjsws6ncjcXLZgqwQxX6VPGGPOuiJjD2KdOf/krAbcQUNAJ+6Mq6tqVwNrrcGLVUOh+QjiBB5j2oHp8qTB+3C5B5I8IlB64JmK2FjJhDzhwSxzZeBRIP5GEot5CXeePNTuY6OnqCe5U+yM7kAA8LrVoO926n8a47SxfNwE+W5TgvEyV1h96Z44Hq5Q2cLAIA27q8aNcOnB1eePi5o3cx1g2qWcsLU41/D+ZgbT2RxEcT+ZelOde6tYpZ/co+gYRrq6vPrw5aDUKEHNn5GFhODE9CmFJzTgTJaaeV2pBFLphbfjTrEaAcAjiAcsOmZv8puXBw/Ps0qJ93JMT5NiaQNvAC069bUpjBUdQD1LLm+ivQp7eSLx9rdxu70g2vsY6yOC/qhLMnOJH+hjIx6CPrCt5nQA2sImmCn6MOsgTqsy5H68KfsEln6B/RC5E8/1pToDWeG7vhMrqt7Oyra1mtV4xynsdEsxtgquAQ/+kK5PzB+of4AxVqPyfUbA1Zc4yrnbo969s5egkVtByuVr968PB05RiZYpjnxhLBSMEDqqP+bI6gZ4ixLWAfgZXYB6q/b8mz82zyPs7eWuGvxgAx0E6H7LvN+iPuOW1v1kdKPvMPanRBcLrsnzHN5J3In/4+VbTWVYIsHKyLVaoQuftNXqOGnafdbHeMl9Eqp0VIFgo9f6vPqza/VUcnx8d+JrpgHir5L4ygH6+fJelN/knpQcYT32glIIjw8yPqSuD2VwqpcyHrpppXu1Z/QeC1JI8lIUnLeDbm3cswdR92t4b6Y0MjVdr2aI/zKyplTr2+7CX/1PRrvsmxr4VY1aMJKJj1KH3i94BUUpmQqg88CFuIkPSraAXSSxIkjwXU44p5L/yH06LUq8LrqDvtWcFYpKvYqcBfY0yieihLl8m+F8cRQYQ2yFjWb8HN8mxwGa34u2qt0zmrX/y56IccRmWYkT/9PUemkOJ6es3YssXzg71/woJm14FTaXuQ4yb18iDg9IMEkPJxxVAevPGQAg7CHMYPpa/pjBKf89CxWJ1INvcO+sGTP/soLZh+9PLFEMB3qiXwGQS2W6FNbGUwpobl6BPGTdcZodz0CkFsjuQB7MfxdguRfR/kXc2em4kBUh53E5ffxxid8fuArZY3g+3xZTsqHemhrPFxuCewFu9cSy64l92+1umsZyeH20rsJK2o0T82/7etl6wHUDXbmL6qvJIes1hDl0yDUrIeAVqKjOXnamOyNt1NyIVzV32bNBSRphlvtMbbLDWb1lub/eLKOn1KoLdohbCeST0Q/d7CTEGhmErXq81cGF+Qquu0PflvYeiZFXez9I+aEjLqKt8G X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2024 18:04:18.4166 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 76a0ad8e-ab59-47e6-6bd2-08dc96d3907b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6301 X-Patchwork-Delegate: kuba@kernel.org From: Daniel Jurgens A new capability with more bits is added. If it's set use that value as the maximum number of EQs available. This cap is also writable by the vhca_resource_manager to allow limiting the number of EQs available to SFs and VFs. Fixes: 93197c7c509d ("mlx5/core: Support max_io_eqs for a function") Signed-off-by: Daniel Jurgens Reviewed-by: Parav Pandit Reviewed-by: William Tu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/eq.c | 4 +--- drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h | 10 ++++++++++ drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c | 4 +--- 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c index 5693986ae656..ac1565c0c8af 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c @@ -1197,9 +1197,7 @@ static int get_num_eqs(struct mlx5_core_dev *dev) if (!mlx5_core_is_eth_enabled(dev) && mlx5_eth_supported(dev)) return 1; - max_dev_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ? - MLX5_CAP_GEN(dev, max_num_eqs) : - 1 << MLX5_CAP_GEN(dev, log_max_eq); + max_dev_eqs = mlx5_max_eq_cap_get(dev); num_eqs = min_t(int, mlx5_irq_table_get_num_comp(eq_table->irq_table), max_dev_eqs - MLX5_MAX_ASYNC_EQS); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h index c38342b9f320..a7fd18888b6e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -383,4 +383,14 @@ static inline int mlx5_vport_to_func_id(const struct mlx5_core_dev *dev, u16 vpo : vport; } +static inline int mlx5_max_eq_cap_get(const struct mlx5_core_dev *dev) +{ + if (MLX5_CAP_GEN_2(dev, max_num_eqs_24b)) + return MLX5_CAP_GEN_2(dev, max_num_eqs_24b); + + if (MLX5_CAP_GEN(dev, max_num_eqs)) + return MLX5_CAP_GEN(dev, max_num_eqs); + + return 1 << MLX5_CAP_GEN(dev, log_max_eq); +} #endif /* __MLX5_CORE_H__ */ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c index fb8787e30d3f..401d39069680 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c @@ -711,9 +711,7 @@ int mlx5_irq_table_get_num_comp(struct mlx5_irq_table *table) int mlx5_irq_table_create(struct mlx5_core_dev *dev) { - int num_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ? - MLX5_CAP_GEN(dev, max_num_eqs) : - 1 << MLX5_CAP_GEN(dev, log_max_eq); + int num_eqs = mlx5_max_eq_cap_get(dev); int total_vec; int pcif_vec; int req_vec;