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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Daniel Jurgens , William Tu , Tariq Toukan Subject: [PATCH net-next 01/10] net/mlx5: IFC updates for SF max IO EQs Date: Fri, 5 Jul 2024 10:13:48 +0300 Message-ID: <20240705071357.1331313-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240705071357.1331313-1-tariqt@nvidia.com> References: <20240705071357.1331313-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A4:EE_|SA0PR12MB4445:EE_ X-MS-Office365-Filtering-Correlation-Id: 6799c171-ef56-4c2e-4bf9-08dc9cc23cac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: I2YY+fxFNq6Si7VKk6q8QLyHSWW6/T5VsTkU/475rG4P4XoPyjK48svySRCIC/JgeikLV4KCDAfjAZr2Aw0/sWnEIzEjqB+xmk85hXVQoHjmftYOHnyoQaecWGcal85nuhQkoT4u+QLSVS4ocQbFRSIHee+2oTYW4MBN/FNrsDQX6S1iv9w8tCeYeYDJv5wFAMQR101A2CdFT+6q8RQtYl+2kltxAhnidBXwbLUEWJFInWVJiPs+kElQxbf/Bqf4GR1RK1s2J/4oO8TD82L17IyqMVFcyeYY9wGWxwpqBtjuyH43rFRnbJQzJLwp3tHY3Hp0QjJ9DRB56frcCoiUVKRS4vFl44LH+BJREPDpex7xSOpc1XY5BO0hdG7bi0urmOvQ+SXby+KqWZWzm3taoXkV3HuQfiU4p0n2MCQ3BZmZWxwRzDufMpwX1eAtcyTZOat0KPFr2FOncDbfzJElcCWLs7ehK7N5xvYMLFSu7v/48SzpbmUeL8kgE5T4RBIxTxHmCxJU4G4eDTio4YV1zll71rsWpoPiBo0jYGhuq2yxyqubMmoKdoAB8nVaOLhlaKxUyGnNoeqyGKnHD5dylaFqm/QlNLsRYxJMdfDvjxr+PC/5R9ipCOVeUwRX+bwNDe49HfzTdItFFXv+pWkp+6IhZQcreE7qcoICCEABpFoMZCVlzkwpKbxL5M2eniuEGopaRmTTT9vWPUEXItljy57Fu8GJKfs5may5lRgAfzGnif7NF3WXLmyAg8nPBxTuSB6+yLJJquue5KEAe7Ywx37GVHduTKiqNBLIhVoETlPKH1G90uJ3U8Y3rh9/2u90lk2TtVVuCKQnlOgoXASY1HzN7j95cMaI2jHPAF9O2v6y0FYubb7YTSHUckFLpOZxgJTbMDmk0ngYIaYw6ud5DkvTT7gAEUhFbn0j0JJtbJtH2WLHe9MUZEb5ASXU9VWTydbwJ2vix7TjyWsYh4XBsBmNudtrqbj09+ybkbQ1TQtryuZN7PykceY+Ahm0p5+1+9zEL96NhwtJbBKkMCdkRy++UCsPctbu0GG5kJFIoVbZKIJSci96t7nEsFi25yc/V0bwJ0QZSsZFp4c+lvS2CslJK7yM4866gLBW/jsp1qDd9104zB0Bp30MIkVM5zo3LLKpycj7sNJAkA2IswMiw91cELysNOGLOIjt0Zi0nc2c2E/XqwZ2BsH7bWG4HtPWPvwshSgmrZoWEm/zoBC7t9l6h/qmb8Dn9BxAJ+8JOMNkcjnPm7IzOLi0e+9hiy081MkZq8LKKBnW4SCmqbmIyWi9Xj/cYvVlcHHu2YoFZTIdUMgNRyx1M4XKDo5xW/i5LJKJ5bay3TxFAGc6hSgXHfv1Oj4/7iie0TuCeotmMZFn2ht6+Cn3URb4qtG24WeF3d4yX+0SJlF/5u/TvJ9iiblhqMcf5ErWp8w145hXv1+8t4s6Fj+K5oVxoQpPHRET X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jul 2024 07:15:23.3874 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6799c171-ef56-4c2e-4bf9-08dc9cc23cac X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4445 X-Patchwork-Delegate: kuba@kernel.org From: Daniel Jurgens Expose a new cap sf_eq_usage. The vhca_resource_manager can write this cap, indicating the SF driver should use max_num_eqs_24b to determine how many EQs to use. Signed-off-by: Daniel Jurgens Reviewed-by: William Tu Signed-off-by: Tariq Toukan --- include/linux/mlx5/mlx5_ifc.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index fdad0071d599..360d42f041b0 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1994,7 +1994,9 @@ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 migration_tracking_state[0x1]; u8 reserved_at_ca[0x6]; u8 migration_in_chunks[0x1]; - u8 reserved_at_d1[0xf]; + u8 reserved_at_d1[0x1]; + u8 sf_eq_usage[0x1]; + u8 reserved_at_d3[0xd]; u8 cross_vhca_object_to_object_supported[0x20];