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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Carolina Jubran , Tariq Toukan Subject: [PATCH net-next 06/10] net/mlx5: Add support for enabling PTM PCI capability Date: Fri, 5 Jul 2024 10:13:53 +0300 Message-ID: <20240705071357.1331313-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240705071357.1331313-1-tariqt@nvidia.com> References: <20240705071357.1331313-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD4:EE_|CY8PR12MB7634:EE_ X-MS-Office365-Filtering-Correlation-Id: d39ce388-a419-472c-92b6-08dc9cc24aee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: M6FKk1gRNphB4O0M/eSx0xKEriN6jXlEKOR1HRq7pBcspIPxlvtc6+n5iIPfX9/7NnN6FKHcy0rZIyforboRWfb2ZQ6X846jmg965ZhsR4QQZP9T3O9jASdmid/lrLguMBvL3ED0mRyw66NyAhdKyWmJaXUgil2I/m0/yUV9Y304vVlFXwr1ewrY0Er7oSOSaUtd5YPnxd7W6B4VYnHnlTYVnp7QfbS4kvMVtRJTkstMV0u17HPrx9SRl15Gpi3TD9FKOtPMnK6XOU6Jxj2L4Az/TZfZ27JrcPdcE4PXrOi0HUOtYzpl2htKvKsmnBwVl5X8hw6AvU2U1sjHnhR4d6VWidZw7bucicKhFm6mgxXoF+rOHuLwiFoKzEtVX+rPH7RjXKu1ZFSlc92bhCKGF2ask8+NMPDQ5770+FZOAU9+iq7x95V0UgFiGSpIZcKY5g86Rcr+z2q4Rt0la835cecwO2OALuv0OuckAoeAQchNPomkLP7D5xO/BEAw/ac7Xr515qePgUJys4Q1WZ61dhZBR7aHQV+hC6agcGd+OX6jPzUy4LMcUBEJvNYg8sBcx0OxvBWO7BQ/OlNQwYt3XtLue0pjBbga1EiAPUVd2Uo6XvHOUO239ddHTXbWs0Bih9b4qTtd57e/sLsklW0HH7i8/myDeJn94+VxSmdlzCjb2J8TLXlAklWtS7SXvlrhtY0GTN8qz2jB8uZW1+3g+xCCGakmBvmJPVWsZjIaIclpjyboM7661rj3gLyirervOmfhsK62qWqHx0aCJuroTS31UUNeqMbEfaHbwQnP9VN2SHYe1MNmmT8upf/6Xc66djZNBUqvthQuDpdunqTvyycoVuVwYCAYXbMzYJZWw/DnOA38r9OO7QAWjeSMHp81pTSzsGnET4ND735hV3eRuK4EyMFxw4JwgQjshcnpHH9gzQ/1a7IuABfdDhVekRjG+PY7NVxz73uLi5AUIaNwdNNfLFuf55bbIm0rXYGJWPv2jfgSM7FdI2eyIY6clKgwDBQtkIj6VPqCHkzF08KwH0dYd9NA8sJcJhXp/dbDWGFf+8lpTWoVY6Nki4sdm8jKg8frqIzbkuoBHfaoYqWuUXGBPM+d/6aKLd+PmrNLJnKiqzk2KngpdFG+zi7EdxHWbo6SLfHosaiLCWS0PWH3gKt/5RazgwswkXwftkNNhrQQ7gFmbVeCb9OFfU1CjvXwgu19DkA0mC0vZwcV4rLO82iEMJHIUl9lahUgdieFwLJGCdJChmbz1efs425NS6r4aJ7H3zGHAmp1GBHx9W7vpJX/DQ+xN9j1do/YGKbOSDnjSd2r5C2wPtBhLi76L4jAOpGoAgTSPsR6F+wP03rT74JlnZei/KP4FrQrhaKgYnHaahL+kgPWJWl8Bvknvs0mL1ESJCU45dVqyVwUei0VskHhps91u6F/UWSHhVeApkiOQbR/eh0BW99EAyOAaHY9 X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jul 2024 07:15:47.3567 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d39ce388-a419-472c-92b6-08dc9cc24aee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7634 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Since the kernel doesn't support enabling Precision Time Measurement for an endpoint device, enable the PTM PCI capability in the driver. Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/main.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index 459a836a5d9c..31a43e0ee57f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -923,6 +923,11 @@ static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, } mlx5_pci_vsc_init(dev); + + err = pci_enable_ptm(pdev, NULL); + if (err) + mlx5_core_info(dev, "PTM is not supported by PCIe\n"); + return 0; err_clr_master: @@ -939,6 +944,7 @@ static void mlx5_pci_close(struct mlx5_core_dev *dev) * before removing the pci bars */ mlx5_drain_health_wq(dev); + pci_disable_ptm(dev->pdev); iounmap(dev->iseg); release_bar(dev->pdev); mlx5_pci_disable_device(dev);