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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Rahul Rameshbabu , Carolina Jubran , Tariq Toukan Subject: [PATCH net-next 07/10] net/mlx5: Implement PTM cross timestamping support Date: Fri, 5 Jul 2024 10:13:54 +0300 Message-ID: <20240705071357.1331313-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240705071357.1331313-1-tariqt@nvidia.com> References: <20240705071357.1331313-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD7:EE_|PH0PR12MB5606:EE_ X-MS-Office365-Filtering-Correlation-Id: 5008a377-f9f2-4e87-2674-08dc9cc24dda X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: BJJpMkfDTiiTrPcf9I0qymlK8pmrXU60Wu1qoMG8vVx0w5943CLFSOiLXcQrPo4qYlJoqrqV6lfdNex/xEHSXO/cmV/rPzY04ft7ULLOOMmmxs0cPFM1Ye6AJ1vbi3C2rPtxNrACsIG8lYyWomuJYSFanduNs3foVBxQWmOt8JXbqMtCn9Wet2MZ0cZCoDjA6OmbY4Ks+gGTf1eJb7ZDIJMZCVAH65qRTXV+v7x2TqqOLHCDm/sNIqudywE0BC1NErD5ddfyYOipaYZqV5q7Uk6qAl+wFasRn2HHH9rGzRpQVECXEc2hX0KXDXBg5N6ItK9TrgETum0KDF0WH5KJrmo3opBDBlNuxpAP9BLk30Kx9ifjdalo/vthx8zgIoLA0PCW1jc+i03sLHCVkqBGnwVbMvZE5MfsPLfVw4+qpFZxzDPPbY/EMvv7ImOO9jW0Ky4XnGh/zFzH66w7NHJJ4NxiP5+gTpCZoN54Kelg3hF3RcTWQXvrZfovNH+8eRh6de1TaQ4cXN64TDegQg4WUaVvAO5WElOLsH6aWKgU4Pe33L3FqajNpbuW3L2fxTJnktKXq/b148h3VJ5RmeG9V8wqt3qG29o4fbT61XHtO2oNLz3IoIn6w1LLeg9qEACT8viI03ynd3VsEJNCvXyb2q0IDNWpA77bBo5ae8HnRXU6Wbn5MCyPMqZzYl0NbHHLIQuVkfMFjS/sJe7QEBt4OPhYzEtjdfkdfVX4cVkS/rtAHaUn0pSmskOj9refx2LOjt6Vh2XohTLuwcQPvR2nCS+q9hahtymAr3y3VObqZQIEXg9Iz0/hPRiWWlikw+u7GUUZlQJJAOWCbK1bqMvITRVSbj4+jTzdqKiWld95g6WphmmRx//pRuog6tvGW0G9aXQ7a+lkGAmqPfoYeGLVSvn/PR9ABCKusZIbZ+CbgmVWwu9ImSHZTipUdDlqP2PBtjpML9CVE3GzfAqbQnxEij0N/ycguJIFewriPS6drpUfyKBVxqjADy0FF2opfenz9zFidm75hfXPblQvMiBdGYtK1rrxUyZd2pJrumCthFMH4czhv1Ace5ZSeXtVrIvXmoLyNlFmv10+x3Rkz0EYez7BJWXLb9BOmCx4qqi7nfABD54Yfo+FRDqXS5NkGdG4m3eofxY7NNxTGHJx57Vj2ehx6BGYzVTVy+83SMnOqqTp1Ghn1mHE4qAal340hMZn+TxFWCGOZo2xdv06phRy1R5R//Seyew56LJBi67Fa/pQaVBc3VwSjNM+kFlSOY6KZxTWBzbU7c6/4KjMwUpI6rpg789dlU+V589bdSjDs8mn3iAaoeWa6aH421BrBZBWIdayY67wLpIqndqrG/bxr6bDLLtcju2iPdl0hLp0+Yri2hH5gn3ZOi9loM3Jc70K+qyxv6PRDG2EIntTdFFdNtVL4nDIN8QPgaaxvwM3ZeFUN3iOcROHHcrdFbzlKEMk X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jul 2024 07:15:52.2404 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5008a377-f9f2-4e87-2674-08dc9cc24dda X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5606 X-Patchwork-Delegate: kuba@kernel.org From: Rahul Rameshbabu Expose Precision Time Measurement support through related PTP ioctl. Signed-off-by: Rahul Rameshbabu Co-developed-by: Carolina Jubran Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index 0361741632a6..e023fb323a32 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -30,10 +30,13 @@ * SOFTWARE. */ +#include #include +#include #include #include #include +#include #include #include "lib/eq.h" #include "en.h" @@ -148,6 +151,83 @@ static int mlx5_set_mtutc(struct mlx5_core_dev *dev, u32 *mtutc, u32 size) MLX5_REG_MTUTC, 0, 1); } +static bool mlx5_is_ptm_source_time_available(struct mlx5_core_dev *dev) +{ + u32 out[MLX5_ST_SZ_DW(mtptm_reg)] = {0}; + u32 in[MLX5_ST_SZ_DW(mtptm_reg)] = {0}; + int err; + + if (!MLX5_CAP_MCAM_REG3(dev, mtptm)) + return false; + + err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MTPTM, + 0, 0); + if (err) + return false; + + return !!MLX5_GET(mtptm_reg, out, psta); +} + +#ifdef CONFIG_X86 +static int mlx5_mtctr_syncdevicetime(ktime_t *device_time, + struct system_counterval_t *sys_counterval, + void *ctx) +{ + u32 out[MLX5_ST_SZ_DW(mtctr_reg)] = {0}; + u32 in[MLX5_ST_SZ_DW(mtctr_reg)] = {0}; + struct mlx5_core_dev *mdev = ctx; + bool real_time_mode; + u64 host, device; + int err; + + real_time_mode = mlx5_real_time_mode(mdev); + + MLX5_SET(mtctr_reg, in, first_clock_timestamp_request, + MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK); + MLX5_SET(mtctr_reg, in, second_clock_timestamp_request, + real_time_mode ? MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK : + MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER); + + err = mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out), MLX5_REG_MTCTR, + 0, 0); + if (err) + return err; + + if (!MLX5_GET(mtctr_reg, out, first_clock_valid) || + !MLX5_GET(mtctr_reg, out, second_clock_valid)) + return -EINVAL; + + host = MLX5_GET64(mtctr_reg, out, first_clock_timestamp); + *sys_counterval = convert_art_ns_to_tsc(host); + + device = MLX5_GET64(mtctr_reg, out, second_clock_timestamp); + if (real_time_mode) + *device_time = ns_to_ktime(REAL_TIME_TO_NS(device >> 32, device & U32_MAX)); + else + *device_time = mlx5_timecounter_cyc2time(&mdev->clock, device); + + return 0; +} + +static int mlx5_ptp_getcrosststamp(struct ptp_clock_info *ptp, + struct system_device_crosststamp *cts) +{ + struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); + struct system_time_snapshot history_begin = {0}; + struct mlx5_core_dev *mdev; + + mdev = container_of(clock, struct mlx5_core_dev, clock); + + if (!mlx5_is_ptm_source_time_available(mdev)) + return -EBUSY; + + ktime_get_snapshot(&history_begin); + + return get_device_system_crosststamp(mlx5_mtctr_syncdevicetime, mdev, + &history_begin, cts); +} +#endif /* CONFIG_X86 */ + static u64 mlx5_read_time(struct mlx5_core_dev *dev, struct ptp_system_timestamp *sts, bool real_time) @@ -1034,6 +1114,12 @@ static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) if (MLX5_CAP_MCAM_REG(mdev, mtutc)) mlx5_init_timer_max_freq_adjustment(mdev); +#ifdef CONFIG_X86 + if (MLX5_CAP_MCAM_REG3(mdev, mtptm) && + MLX5_CAP_MCAM_REG3(mdev, mtctr) && boot_cpu_has(X86_FEATURE_ART)) + clock->ptp_info.getcrosststamp = mlx5_ptp_getcrosststamp; +#endif /* CONFIG_X86 */ + mlx5_timecounter_init(mdev); mlx5_init_clock_info(mdev); mlx5_init_overflow_period(clock);