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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Daniel Jurgens , William Tu , Tariq Toukan Subject: [PATCH net-next V2 01/10] net/mlx5: IFC updates for SF max IO EQs Date: Mon, 8 Jul 2024 11:00:16 +0300 Message-ID: <20240708080025.1593555-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240708080025.1593555-1-tariqt@nvidia.com> References: <20240708080025.1593555-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002322:EE_|CY5PR12MB6225:EE_ X-MS-Office365-Filtering-Correlation-Id: 7ce7b30d-1b6e-4709-86dc-08dc9f24361f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: eMbB3G+hzTco9iMFc6W0JFYweM8qz3osxO9hL/kWHZEFwZ3eadYlRMSscUUs5fjokwpdRw7ol14v/1JIxcPWeNMbNd17NQl1lTAdKNnae/NK3mkcTkZkOrBSgGvWJ6XEgBClGlP9Bfa5jyYrBQidmv7qjqq1ZsoFe7HzOtK/TH/wlpBKIxoqsyNxe72SVgaEI8QaqH8gLpOQ32B8sqplVBaaLp8SKqOuOokCOl+OP0qadYaeWeOVezgl3Qy+Idoh25eFi8dmTZi48cwSWv4eGG/dL5iau8p1sDEn29OqVB2Y/Zvb+Q+W8A3pAqCYXSP4gbY1zuQNVd0lS9xGsf6codIaP83hkdKrCGlIhGHuCDTPreDWeCKM04rgmgG4h1QRyEv9oyd2ac2zWQjfckPlI+qYQmlalE3j0ZMMZB0xZDD7SYi6QwnkUpdzErLu2poj7WERQFd7tdaPhoxcT7H2nEpo+Up49NAMh/T7XnVALnXGsGstNq90rBfEd2BYbyNGxXdpXzfz9Z6EdjzX1kGLaPn5MyOuuiqmrdklwYW1GrMeoJB61TV9LmNPfWuDZKHbr6oCeAML+wM0cedAjRAJUmdiq12bmhELoMGXsIxnDBOqleFTmFD+LxkvrdBkAP77n/ajQj8KVbg2Q+PRbCarsjLDu3akzH6sW6gXbmrTT+/gilByrSRrYQYnbDzWEP9Iy2ZBW/ehOULS/Z1HXiEaMz3XO4j5EBpTC8lmFyLHhtm06Jm2zHuzQFZe3h8dkeQi1M5J0cKj1MH98eXz00AAJ9lfG8deGDNDDSzn59/Lv6qusVIEWuIt1KkYwJeV4E+zqk2BgtQOITXs2hk+XE6LyCZFic6/r8Ot3xhPNnVLmRN4uROC7jOvAksl17Ij1EeCbyuNy52ebs+peX/7ke8da4mDXw0YyTLGGuUYdO6SGH/khS7fJtldMB1ex4XiK/TL0QVBSr5gHPwEF4vkgSQRcVndIq0DvC5chT5D4wJX/Pni3+1uKeOzLdGBwjkqrNQUNBAPTeUnZgQGQyiW1Kz8XawpBZxC+YTm5dJJ7ke5qSJIoyp/pnWLIbir3ZRxljt7zh34YJrlCpk2WPXttPFO2vuekMt18i2XxxxvtRtPSGsRnhh7NxK+Sidp0wINUxrOhqbiDATK2uwA5rG+rTs+Izqh2tZH//TbaR9e5YS82m0js/h90rATgkHWzqn7hekWlZRhbRFirx7duC7J7aBRuqbtW5RGX3yjFkxAATff6X4HIiJoWyAZ5jUQviJzaZqpfZXrTnNK9yN4a+loDU/ZZH8YKwgJvioYt2DWs8KdN5JdTRy/6ZtZF9xye9OKHT2TshfC8QQYG8Y6PgzJz5fpa4NayyLoCjmjbJdlaUPSCiw05gMSiBi4coHCkmu0aEG9AKrSIeu42QLA+vVPKDUQkXMRmitos8hov9oE/xAJPIRBDixpegik1dIKGjYqV9dZ X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2024 08:01:45.5286 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ce7b30d-1b6e-4709-86dc-08dc9f24361f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002322.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6225 X-Patchwork-Delegate: kuba@kernel.org From: Daniel Jurgens Expose a new cap sf_eq_usage. The vhca_resource_manager can write this cap, indicating the SF driver should use max_num_eqs_24b to determine how many EQs to use. Signed-off-by: Daniel Jurgens Reviewed-by: William Tu Signed-off-by: Tariq Toukan --- include/linux/mlx5/mlx5_ifc.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index fdad0071d599..360d42f041b0 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1994,7 +1994,9 @@ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 migration_tracking_state[0x1]; u8 reserved_at_ca[0x6]; u8 migration_in_chunks[0x1]; - u8 reserved_at_d1[0xf]; + u8 reserved_at_d1[0x1]; + u8 sf_eq_usage[0x1]; + u8 reserved_at_d3[0xd]; u8 cross_vhca_object_to_object_supported[0x20];