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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Daniel Jurgens , William Tu , Tariq Toukan Subject: [PATCH net-next V2 02/10] net/mlx5: Set sf_eq_usage for SF max EQs Date: Mon, 8 Jul 2024 11:00:17 +0300 Message-ID: <20240708080025.1593555-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240708080025.1593555-1-tariqt@nvidia.com> References: <20240708080025.1593555-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E61:EE_|MW3PR12MB4410:EE_ X-MS-Office365-Filtering-Correlation-Id: fa5a93fa-ce03-4e8d-631b-08dc9f243b9f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: 1uXeyHwjPxZSFu3LtGf+TIgJik9wJINMQgQGRFB2HRy/Beu1SuhSar9+34o0g0uUigc+75p0TDyBoOPqAV87CSBrGea5o04yTRypaM9d854NY1/GcsRAPlgOHUUmZqxMyf4+IEzq+knnZFCm1qr1yhfIUVlT+cMKDLmR8LwOs3bpP0xwblyvm2KWv6y3vWNR6//CrRpFM8zlpElUQiCYDUAG/3H9Qkrbs/L9K1JUhIE5g301NURMAgFGiR+6hvrQx3INZLJ3ehUe7VWIQ1MvidOuH/HxBnB0ANkY/axv6PhRFgeHaAqgvRsUjBcfQWxN70SlnZJFiK2Kpii1dZICikq6TKyekn9/xFC5Kd0xj1vuJraGrRwDLd8qoaxiVoxuhhLf2t7DxBf++q60xTV+I6M5XA7LnvsCy5yd1h4tGTX21jmBsi+m+xcQ0IC2wAVPLFxn9sGihPaEBFuHKEcNHp8svULlbXxIvD3R1H43V1h5y9GBITudu3/QR9zxd/Z5Uigs3Y4vewy7b0etWezLbfHtwtbfmMrv3+J8VontF4H6PfWVm6m7a6fxBVAd+GC4fk1rkPHS2cG3Jg49wkAiDXknQhrLBPwYXEZKPGh+f7dDzjvzXgf0XypznROndQlWHKFgYcW13v05vsO9otL/CKYnCix5dcXwFm+3lfu285cHkAeuR4Kmy0uLt5W7ghYFAjliNYhbSWJnuBGa8VDnN6pPm6UWwLiMx2DlS12diaJKzyDlu+c+g66DSKbFIBeTMhHH8ZC88GCMxCln09GGe88nZfD5TRMoYbme3lZUZ/QeI7gHF5gGSV8DG0yRpgtdhwhVcbbWmZKkUuDqDg0BW7kEbiKXLyBFyhzwOYrz/ZXYRuW8gyDMxjdTzQzc9WiLQSrohbXPm6/YKt1KAClCd60YC1R+L1igtzhZzyWFQ04fsAGdhbqlcEfAkpPJ/WzfHue6oUG/rXdbCSKOJOR/kfB67tCfsX8/n850XbW9h3qhrz1j+iooentnuJum7tIVheR70D1gPOmyOb3T6i3Bl2NVVu0DrLH9eduBwAOICuD1uHjbcccZzWJNZhs8pt0goWtxc2sFw0WUwlJPsCHlJ5G2CZioAgenbwV0/LF15bjAJS2L413JfwkbzolZCELr2H3wR5bh4YW2Qk2CNJ2YeUDpCPRizzqnH0fdGmtYNrJM/fgW19V65v/VsN3JnGJp3UJujlhtgVV/kyA7vW/oLAlZoixgfBkfjDYzvCqON3ckjSQEJiglLycfCbLmwuTaZbHwUGtPqXFkW74kQQKO+tv8LO2I+bzAUw+jA6a9nr+MddHjUE3RshS4zZJ3P/NigK8A3sO/xzr6LsScpZNUIZxJw3kYt+Wuv8YgSXF20dWuG3xej83jGiMEuvHHT0GqKFXGs84Ju9Gs9n1hX4HYL9wvAh+Vhd/dvT07kZXCyuzuGA5Bcy1t4LjR2zalKlfV X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2024 08:01:54.5520 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa5a93fa-ce03-4e8d-631b-08dc9f243b9f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E61.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4410 X-Patchwork-Delegate: kuba@kernel.org From: Daniel Jurgens When setting max_io_eqs for an SF function also set the sf_eq_usage_cap. Signed-off-by: Daniel Jurgens Reviewed-by: William Tu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 72949cb85244..099a716f1784 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -4676,6 +4676,9 @@ mlx5_devlink_port_fn_max_io_eqs_set(struct devlink_port *port, u32 max_io_eqs, hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability); MLX5_SET(cmd_hca_cap_2, hca_caps, max_num_eqs_24b, max_eqs); + if (mlx5_esw_is_sf_vport(esw, vport_num)) + MLX5_SET(cmd_hca_cap_2, hca_caps, sf_eq_usage, 1); + err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport_num, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2); if (err)