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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Daniel Jurgens , William Tu , Tariq Toukan Subject: [PATCH net-next V2 03/10] net/mlx5: Set default max eqs for SFs Date: Mon, 8 Jul 2024 11:00:18 +0300 Message-ID: <20240708080025.1593555-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240708080025.1593555-1-tariqt@nvidia.com> References: <20240708080025.1593555-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E62:EE_|SJ0PR12MB6783:EE_ X-MS-Office365-Filtering-Correlation-Id: 5aa4b015-d1c7-400e-a2ac-08dc9f243ea6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: QenT207SjhxTospazoszP07jiZt0cCA1ARHFi0amZEtAkjTeJkX+q8Zqcc6fMSwBfdP8cC5+ZDFYL/CR4qt9xZ126UOqOAsfDsgymUKLZ2HV2WR6EOkN1Kpvtmuzr48Y9Bw8SejZkajlqR11BU1v8RkE+aggJpEiiuA0GA5HCgr917pmMHeAJEl9G3geeBaUbqzpMW5DLi2rmqL/ApSSW4w/ZXY3vkzUbKKiWXGLFhgS6PlIe1BTVyualCrwuuyfrvTh/VkgNYDsnYrbzK3lU+vYTf+8csasFjsDI+/AzlL33zHsYPPL17alWpk5X1iF/roqQwSfzi9upWTvhuZt6g8ZY1O0X/oufgR8V6TYyd2GwHreqb/SC5ifHb1D2KJTJ6lVNZA8N+M+5CPVE2Fg7aG66Husw/nJNy48Aary7U8nsyYRKCHtjSpFp7J5ruvu86IkGGi1KsqZMTkDLdD1HCojMXV64Z4oXU9Jok63qnyxflgSXJ/MVPr+bJa5ayfdc9MGIyEw+ziHSzj4cgGko6Gxu9KS4EqMb/kf7t5perZchby5EMxqJoPLJxC8FKdm+LNHiu5fWy0dTYSJYnKeC24RdVQ9pZAS1afXLyJti8MPbP6NAqDptSYO+urZilD0pNGECtF+Pq3VBaLNN2Ty3OY3k/dxDt7qtplSLcpeXMlazdN68uUpcV7FXOuMAAmQcMuCoBU5ePqPAw5imiSLeH+/l7Opog9wjLNhxHHvxlI/eG/DOUbj/XkRzWZ85DerbVGdYmasBm+cK+mxAtlpJ1nPo5DynqURNEljgOkEvJ6JQ/Y5vRi0K9Y6Hqsmr22epEc/DDO4j6WjihgKTtvgDH0BNkAdg4UCI3S+6BMx6JNJkop3C0XVg8y20dXmnW3a3Qk78gyMicF7rTJcQ8x6YwmCJkXwgkLJcAaoOL70afcLZINCPery+FcinIBP5WzEeFgwcZX/UNCTmDY1CajrMbRt9dCF0o7d1XKYgnGiEOenvSABd3y16UHsODITrD9oMobskcQ/VvfQfmbxfk1Y2WhRRVz8Jvw3voadJmvKz8z3ZRgAlkXQazN+ntLf0Ng0MisS/RJmObf6C3Tv5oH/Op0vi5hvmz4q5+wSSSYYmBVmARgp8iAQVRGw5MxYvAkONwV7Ud7bsF1e0izxpsVbHewOFR2ChAFR+WoVr1Rssush92YAPr15xFYkSFrXYB1KM1Nix/x9+i7tnLTNPDyIJj7RGb6cQwikySlKv69TU19VyZOTB/sus0RkxEebTMRHYwxbf1A76T0giV+SkEiZc/+pQn8yQEv1qjpO2UHJTEyeljjxw07HQvjtz1qtFTSfn/zpb+3dD3ISunVlbHbKWBlm9RDlbXTRc8l+v8iee5lUcxea5vmq4MbLC/1AP8aBqZgo8tD/uACCbu+hRsxXsI1B2JW55t2E29opHtHziPQwWOD4u35Ve0gNcQ280bWk X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2024 08:01:59.6483 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5aa4b015-d1c7-400e-a2ac-08dc9f243ea6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E62.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6783 X-Patchwork-Delegate: kuba@kernel.org From: Daniel Jurgens If the user hasn't configured max_io_eqs set a low default. The SF driver shouldn't try to create more than this, but FW will enforce this limit. Signed-off-by: Daniel Jurgens Reviewed-by: William Tu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/eswitch.h | 3 +++ .../ethernet/mellanox/mlx5/core/eswitch_offloads.c | 12 +++++++++++- drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c | 12 ++++++++++++ 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h index 88745dc6aed5..578466d69f21 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -223,6 +223,7 @@ struct mlx5_vport { u16 vport; bool enabled; + bool max_eqs_set; enum mlx5_eswitch_vport_event enabled_events; int index; struct mlx5_devlink_port *dl_port; @@ -579,6 +580,8 @@ int mlx5_devlink_port_fn_max_io_eqs_get(struct devlink_port *port, int mlx5_devlink_port_fn_max_io_eqs_set(struct devlink_port *port, u32 max_io_eqs, struct netlink_ext_ack *extack); +int mlx5_devlink_port_fn_max_io_eqs_set_sf_default(struct devlink_port *port, + struct netlink_ext_ack *extack); void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index 099a716f1784..768199d2255a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -68,6 +68,7 @@ #define MLX5_ESW_FT_OFFLOADS_DROP_RULE (1) #define MLX5_ESW_MAX_CTRL_EQS 4 +#define MLX5_ESW_DEFAULT_SF_COMP_EQS 8 static struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = { .max_fte = MLX5_ESW_VPORT_TBL_SIZE, @@ -4683,9 +4684,18 @@ mlx5_devlink_port_fn_max_io_eqs_set(struct devlink_port *port, u32 max_io_eqs, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2); if (err) NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA caps"); - + vport->max_eqs_set = true; out: mutex_unlock(&esw->state_lock); kfree(query_ctx); return err; } + +int +mlx5_devlink_port_fn_max_io_eqs_set_sf_default(struct devlink_port *port, + struct netlink_ext_ack *extack) +{ + return mlx5_devlink_port_fn_max_io_eqs_set(port, + MLX5_ESW_DEFAULT_SF_COMP_EQS, + extack); +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c b/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c index 6c11e075cab0..a96be98be032 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c @@ -161,6 +161,7 @@ int mlx5_devlink_sf_port_fn_state_get(struct devlink_port *dl_port, static int mlx5_sf_activate(struct mlx5_core_dev *dev, struct mlx5_sf *sf, struct netlink_ext_ack *extack) { + struct mlx5_vport *vport; int err; if (mlx5_sf_is_active(sf)) @@ -170,6 +171,13 @@ static int mlx5_sf_activate(struct mlx5_core_dev *dev, struct mlx5_sf *sf, return -EBUSY; } + vport = mlx5_devlink_port_vport_get(&sf->dl_port.dl_port); + if (!vport->max_eqs_set && MLX5_CAP_GEN_2(dev, max_num_eqs_24b)) { + err = mlx5_devlink_port_fn_max_io_eqs_set_sf_default(&sf->dl_port.dl_port, + extack); + if (err) + return err; + } err = mlx5_cmd_sf_enable_hca(dev, sf->hw_fn_id); if (err) return err; @@ -318,7 +326,11 @@ int mlx5_devlink_sf_port_new(struct devlink *devlink, static void mlx5_sf_dealloc(struct mlx5_sf_table *table, struct mlx5_sf *sf) { + struct mlx5_vport *vport; + mutex_lock(&table->sf_state_lock); + vport = mlx5_devlink_port_vport_get(&sf->dl_port.dl_port); + vport->max_eqs_set = false; mlx5_sf_function_id_erase(table, sf);