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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Daniel Jurgens , William Tu , Tariq Toukan Subject: [PATCH net-next V2 04/10] net/mlx5: Use set number of max EQs Date: Mon, 8 Jul 2024 11:00:19 +0300 Message-ID: <20240708080025.1593555-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240708080025.1593555-1-tariqt@nvidia.com> References: <20240708080025.1593555-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002322:EE_|CH2PR12MB4263:EE_ X-MS-Office365-Filtering-Correlation-Id: 7e32fdc3-dcdb-4847-d1f5-08dc9f243d9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: oNuynEDcPvASU18uemaDjGXYiKKVwykg17+QmC0/bWrvr7PzRtbtQ+EltOdrxdG3FKaKSNDHEC73D8RWqUI3Zkt5iJPluJH9F8Bmr+BS4mG8fmeVtP1zCivuPv8GTS2TkdWOXF/6IGHs8Y0BIZimZnF7QeyVomX3welkUQvXYPkPHNKrWHhu4lbu2ZubUJczKTMCy87v2HmJrPZ7u/tTgY6qKLLGjOXcDXCKnw85FMt6dR1fX4NSu1LYVNuakwjzP9CKsjMs0VekypVNyhbg85D18Gtr7tcdgbR2LPGNbu/4G0WDUq2n9T4chqqMvQPHwgYncnr5QMC8W4O0g7UQXjZ+6+8xwTvDEbeCoC7rjbjjGzSqYrXwa83EW/qqPWRD8MJbYUq+ZNhKpqw+xkjBirQkX31K5+dcHMSSPHZlj2DHVJWJ53aPG0lqXWrbWcoj4iplk5Sb1UEXotfzmwZY+rO+mggPFClU/O1CEhox0nwfqfh5Tvu//pNEVr08jjGce8iHeC8rVPRne7TXXE3ZhWqIJpPLG1n0WVG5U0c2fJKYm741Nb2JYkaXJJTXGzp0p1IIzS+WC+hLPf0cyF1q3061eCHuxQLFzQngYtphcdLx2rXFutqBkhtFi+AmCtV5Ia+Rb6aD7pqHVkEUDvEryEJKe3IP7Pn/rk9FP2pmsfdlZI6Uu4klNG5E4RwJeJ9TMuzI/P/NDM5ISmUKIvW7D+bSpng6VyO6C3VFSxI18F+FxEZ6C/f3QSF8in56in1HPlAflYM/pTt1Uo0p2XNmTPO/nBBD8mhPIgSqH4uBREFuviomeDnv5QE6ARiyqWJIej6agoA0RYz1LWHU3AmWbekryeI2dF3eVc3WKSU4aagvOJdF3VmvER67YnfhLYxjwLSFLDUUPj0pcBL8zBSQSB+D0p0er/pDcF9Pk/oWAHYKoJgUu8+gIbOgjSN3atBccAUWtQLbC0LVfiSMjvtP1dXOVAppSeGP5BkCG9SR9sVcKwfcEG6EgBOTupKi1JBtf8iEyBmOO2uBlOvTwZ2Vx/HUnFvBIQCVEhDvhpx2wJmQQ0eZ5UiEbDJTE4WtRxn5rFNFIPe1RlyLq0z3DVHY/THx98FAdvRjRNsx12EbediWCx7XpGEzP/KAgjAB4W9KjvY+c/QYG7bBkKuQzpkhicOzgyp2/EkWEARMWUvJXIvz/uzNrPcNfYYl7f3eE0lGOMm9sBh4kKvkpHPngywaSRYIWlEsjOsoFcYxNtcbjf/w6rP6LGEy0CQACdEqHm8kzzh7GdJSEybnOXodK/uEuNM3AdMSs0RMVgY5E5f/5Lfz/0VlBohAOQtQb7dUs0c60R0iZQVcPC+83Gz+o0k9EbfT6vL/MH8YmgGxM9q8NrFhCOlpF3ewIT87pFDxE2JM9ZGxcDswAsNqd8gA2X5MNByIkaOYAQx4rOV9r4snjzvapEXSoIDvCyz5+5DFqluJ X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2024 08:01:58.0912 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7e32fdc3-dcdb-4847-d1f5-08dc9f243d9e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002322.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4263 X-Patchwork-Delegate: kuba@kernel.org From: Daniel Jurgens If a maximum number of EQs has been set for an SF, use that amount. Signed-off-by: Daniel Jurgens Reviewed-by: William Tu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/eq.c | 7 +++++-- drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c | 12 ++++-------- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c index ac1565c0c8af..4326aa42bf2d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c @@ -1187,7 +1187,6 @@ static int get_num_eqs(struct mlx5_core_dev *dev) { struct mlx5_eq_table *eq_table = dev->priv.eq_table; int max_dev_eqs; - int max_eqs_sf; int num_eqs; /* If ethernet is disabled we use just a single completion vector to @@ -1202,7 +1201,11 @@ static int get_num_eqs(struct mlx5_core_dev *dev) num_eqs = min_t(int, mlx5_irq_table_get_num_comp(eq_table->irq_table), max_dev_eqs - MLX5_MAX_ASYNC_EQS); if (mlx5_core_is_sf(dev)) { - max_eqs_sf = min_t(int, MLX5_COMP_EQS_PER_SF, + int max_eqs_sf = MLX5_CAP_GEN_2(dev, sf_eq_usage) ? + MLX5_CAP_GEN_2(dev, max_num_eqs_24b) : + MLX5_COMP_EQS_PER_SF; + + max_eqs_sf = min_t(int, max_eqs_sf, mlx5_irq_table_get_sfs_vec(eq_table->irq_table)); num_eqs = min_t(int, num_eqs, max_eqs_sf); } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c index 401d39069680..86208b86eea8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c @@ -16,6 +16,7 @@ #endif #define MLX5_SFS_PER_CTRL_IRQ 64 +#define MLX5_MAX_MSIX_PER_SF 256 #define MLX5_IRQ_CTRL_SF_MAX 8 /* min num of vectors for SFs to be enabled */ #define MLX5_IRQ_VEC_COMP_BASE_SF 2 @@ -589,8 +590,6 @@ static void irq_pool_free(struct mlx5_irq_pool *pool) static int irq_pools_init(struct mlx5_core_dev *dev, int sf_vec, int pcif_vec) { struct mlx5_irq_table *table = dev->priv.irq_table; - int num_sf_ctrl_by_msix; - int num_sf_ctrl_by_sfs; int num_sf_ctrl; int err; @@ -608,10 +607,8 @@ static int irq_pools_init(struct mlx5_core_dev *dev, int sf_vec, int pcif_vec) } /* init sf_ctrl_pool */ - num_sf_ctrl_by_msix = DIV_ROUND_UP(sf_vec, MLX5_COMP_EQS_PER_SF); - num_sf_ctrl_by_sfs = DIV_ROUND_UP(mlx5_sf_max_functions(dev), - MLX5_SFS_PER_CTRL_IRQ); - num_sf_ctrl = min_t(int, num_sf_ctrl_by_msix, num_sf_ctrl_by_sfs); + num_sf_ctrl = DIV_ROUND_UP(mlx5_sf_max_functions(dev), + MLX5_SFS_PER_CTRL_IRQ); num_sf_ctrl = min_t(int, MLX5_IRQ_CTRL_SF_MAX, num_sf_ctrl); table->sf_ctrl_pool = irq_pool_alloc(dev, pcif_vec, num_sf_ctrl, "mlx5_sf_ctrl", @@ -726,8 +723,7 @@ int mlx5_irq_table_create(struct mlx5_core_dev *dev) total_vec = pcif_vec; if (mlx5_sf_max_functions(dev)) - total_vec += MLX5_IRQ_CTRL_SF_MAX + - MLX5_COMP_EQS_PER_SF * mlx5_sf_max_functions(dev); + total_vec += MLX5_MAX_MSIX_PER_SF * mlx5_sf_max_functions(dev); total_vec = min_t(int, total_vec, pci_msix_vec_count(dev->pdev)); pcif_vec = min_t(int, pcif_vec, pci_msix_vec_count(dev->pdev));