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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Carolina Jubran , Tariq Toukan Subject: [PATCH net-next V2 06/10] net/mlx5: Add support for enabling PTM PCI capability Date: Mon, 8 Jul 2024 11:00:21 +0300 Message-ID: <20240708080025.1593555-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240708080025.1593555-1-tariqt@nvidia.com> References: <20240708080025.1593555-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E62:EE_|SA0PR12MB7074:EE_ X-MS-Office365-Filtering-Correlation-Id: d77c0e9d-4817-4330-3b1f-08dc9f2445b8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: 019VykUV+o+ZxP9ClgcoFCZLjESM1u3F1Cb96KFcMKtqzXYilaF2FrXGrRkLB3nK5T/KcLmQNJdFNuqAOf8vD3DVTuNklZgnGzJmvZL+F0X34kiQpP+MwkHzQC81acMta60Ep119oYx6E/WrhNpf9vLu0jw6ekoQ2uVDP8X+E6blWxD0nLLK52ni+ulEFIGZV26Sd1svYSUFrtyhGAcpz7ZUeYOcT8RnBX2SEDxntiECQ/nTG1iyNaGPVPtsNZ7+7D6BDjeqKQBfzowpDx9ZkRhL9wG7ICKWBVc1ffQyFesNc4l5yE+lHBw/PDruN8dEaViQMROPrVPYlDBx96Nt9zczmCVzjsTh3EIg5DAz7sEYypl41YyF9sXuRbfgIZhghysCzCODo0ZFECt5qJovMjEzIBT4llntIcqB7aj2tmeMBhfeet13TR0JIADKTmSjTvC2g/TaSWLecmydLLfNbBJLBqleIGQ56hWYmZ/XqCMUUBt92LkGJzkGJJ+QOiFyrmEdB9HTvpfSad+OiPKk3971+bodzNESWBy6jFZPPSDOv/m9L52S6pd+elAtKowEHuwd4dmfrhGkk9ULu69so/tRzYYLRJfhD3iwdMmIWEQnGs0/8TW6xg7ZFNob07k38j6sbbfY2yyy2PXsBkEYAUCuDR84hqRiPm264/TacZuH1zAA5T+/G6gqBMeHBvPtYQaGYdTXWvgICMCirVpbq1t098CK7c9zRs5CGUSAfRqU27Xr9fsCxmOvG/PhySaAvurSldEZa051Pi21dcco9U8MZivw6WjSecabAiMjrDsZgUAdaB0a7BFpBkXnzYopnHfnuRlSQbuQK9/KitcLyaZHChDBlykcAKMiW++BgOU3YhkZsHKn2k7RzBob8A5rhW9pGGRWIJXn8jUWgu4cOEdvawW+4+/5EJ4fik41xGjNQCxivYSJUZI7AaJ5rc6eEgrtwjQnXH6pQCdZ6DVD6IDYEKHtNMLN7qY4EdBetbyenxKvhxFBeOVZIUukn6CCWAjY/KtwmbjByyprYv4v+WIlYrYJiyC3pW8C5L7vRxp281rkiNeoB1HkYNqZ+1ZRfXESzCgMv+Y/MAXxTcQqzIHsO0/vin9+M4AvqsHhGB5FmJESIz92RFlhMVlWIoJz0nk4a28bCqWfsZTVMtdoCbjcEqHe1rZRKbHfhlm7FCmPADMV2HNTNG4OvOtRbdD3VAD0P8qqxr0eOCCFFN2Dvnyam2fOmp260R0u2BcVZ6G9W/NF3YsLEz/769c2qKgj3ZZ0Ot/ZISWDcpb5K7e1KRVoXEfGZQgW2OnlrscQYAwttsGY3/SiiiE2iYpl3+lT1XGDFD/dKlMPnOxUWxcMTedKYSJhq46V+6GX0K6LSZXdjWXHVzgrlutCWMkIJTMZje3HD34kA3YLvqxqDtjWBqVUDhOySKubyyMoNhHyz2OqP3vDnxI80vxR3Z3GIs3X X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2024 08:02:11.5077 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d77c0e9d-4817-4330-3b1f-08dc9f2445b8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E62.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7074 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Since the kernel doesn't support enabling Precision Time Measurement for an endpoint device, enable the PTM PCI capability in the driver. Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/main.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index 459a836a5d9c..31a43e0ee57f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -923,6 +923,11 @@ static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, } mlx5_pci_vsc_init(dev); + + err = pci_enable_ptm(pdev, NULL); + if (err) + mlx5_core_info(dev, "PTM is not supported by PCIe\n"); + return 0; err_clr_master: @@ -939,6 +944,7 @@ static void mlx5_pci_close(struct mlx5_core_dev *dev) * before removing the pci bars */ mlx5_drain_health_wq(dev); + pci_disable_ptm(dev->pdev); iounmap(dev->iseg); release_bar(dev->pdev); mlx5_pci_disable_device(dev);