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Mon, 15 Jul 2024 12:28:46 -0500 From: To: , , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v2 03/15] cxl: add function for type2 resource request Date: Mon, 15 Jul 2024 18:28:23 +0100 Message-ID: <20240715172835.24757-4-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240715172835.24757-1-alejandro.lucero-palau@amd.com> References: <20240715172835.24757-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: alejandro.lucero-palau@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D8:EE_|IA1PR12MB6649:EE_ X-MS-Office365-Filtering-Correlation-Id: c4c7fbf3-99a1-4a1b-72cb-08dca4f39633 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2024 17:28:48.2167 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4c7fbf3-99a1-4a1b-72cb-08dca4f39633 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D8.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6649 X-Patchwork-Delegate: kuba@kernel.org From: Alejandro Lucero Create a new function for a type2 device requesting a resource passing the opaque struct to work with. Signed-off-by: Alejandro Lucero --- drivers/cxl/core/memdev.c | 13 +++++++++++++ drivers/net/ethernet/sfc/efx_cxl.c | 7 ++++++- include/linux/cxl_accel_mem.h | 1 + 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c index 61b5d35b49e7..04c3a0f8bc2e 100644 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@ -744,6 +744,19 @@ void cxl_accel_set_resource(struct cxl_dev_state *cxlds, struct resource res, } EXPORT_SYMBOL_NS_GPL(cxl_accel_set_resource, CXL); +int cxl_accel_request_resource(struct cxl_dev_state *cxlds, bool is_ram) +{ + int rc; + + if (is_ram) + rc = request_resource(&cxlds->dpa_res, &cxlds->ram_res); + else + rc = request_resource(&cxlds->dpa_res, &cxlds->pmem_res); + + return rc; +} +EXPORT_SYMBOL_NS_GPL(cxl_accel_request_resource, CXL); + static int cxl_memdev_release_file(struct inode *inode, struct file *file) { struct cxl_memdev *cxlmd = diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c index 10c4fb915278..9cefcaf3caca 100644 --- a/drivers/net/ethernet/sfc/efx_cxl.c +++ b/drivers/net/ethernet/sfc/efx_cxl.c @@ -48,8 +48,13 @@ void efx_cxl_init(struct efx_nic *efx) res = DEFINE_RES_MEM_NAMED(0, EFX_CTPIO_BUFFER_SIZE, "ram"); cxl_accel_set_resource(cxl->cxlds, res, CXL_ACCEL_RES_RAM); - if (cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds)) + if (cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds)) { pci_info(pci_dev, "CXL accel setup regs failed"); + return; + } + + if (cxl_accel_request_resource(cxl->cxlds, true)) + pci_info(pci_dev, "CXL accel resource request failed"); } diff --git a/include/linux/cxl_accel_mem.h b/include/linux/cxl_accel_mem.h index ca7af4a9cefc..c7b254edc096 100644 --- a/include/linux/cxl_accel_mem.h +++ b/include/linux/cxl_accel_mem.h @@ -20,4 +20,5 @@ void cxl_accel_set_serial(cxl_accel_state *cxlds, u64 serial); void cxl_accel_set_resource(struct cxl_dev_state *cxlds, struct resource res, enum accel_resource); int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds); +int cxl_accel_request_resource(struct cxl_dev_state *cxlds, bool is_ram); #endif