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Tue, 16 Jul 2024 06:11:31 -0700 Received: from dev-r-vrt-156.mtr.labs.mlnx (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 16 Jul 2024 06:11:28 -0700 From: Danielle Ratson To: CC: , , Ido Schimmel , Danielle Ratson Subject: [PATCH ethtool-next 2/4] cmis: Print CDB messaging support advertisement Date: Tue, 16 Jul 2024 16:11:10 +0300 Message-ID: <20240716131112.2634572-3-danieller@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240716131112.2634572-1-danieller@nvidia.com> References: <20240716131112.2634572-1-danieller@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017094:EE_|IA1PR12MB7638:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e025253-ee89-4613-b2c6-08dca598d85f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jul 2024 13:11:46.2280 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e025253-ee89-4613-b2c6-08dca598d85f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017094.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7638 X-Patchwork-Delegate: mkubecek+ethtool@suse.cz From: Ido Schimmel Parse and print CDB messaging support advertisement information to aid in debugging CDB related problems. Example output: # ethtool -m swp23 Identifier : 0x18 (QSFP-DD Double Density 8X Pluggable Transceiver (INF-8628)) [...] CDB instances : 1 CDB background mode : Supported CDB EPL pages : 0 CDB Maximum EPL RW length : 128 CDB Maximum LPL RW length : 128 CDB trigger method : Single write Fields that are not used by the CDB code in the kernel are not printed, but can be added in the future, when needed. Signed-off-by: Ido Schimmel Reviewed-by: Petr Machata Signed-off-by: Danielle Ratson --- cmis.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ cmis.h | 11 ++++++++ 2 files changed, 91 insertions(+) diff --git a/cmis.c b/cmis.c index bbbbb47..6fe5dfb 100644 --- a/cmis.c +++ b/cmis.c @@ -928,6 +928,85 @@ static void cmis_show_fw_version(const struct cmis_memory_map *map) cmis_show_fw_inactive_version(map); } +static u8 cmis_cdb_instances_get(const struct cmis_memory_map *map) +{ + return (map->page_01h[CMIS_CDB_ADVER_OFFSET] & + CMIS_CDB_ADVER_INSTANCES_MASK) >> 6; +} + +static bool cmis_cdb_is_supported(const struct cmis_memory_map *map) +{ + __u8 cdb_instances = cmis_cdb_instances_get(map); + + /* Up to two CDB instances are supported. */ + return cdb_instances == 1 || cdb_instances == 2; +} + +static void cmis_show_cdb_instances(const struct cmis_memory_map *map) +{ + __u8 cdb_instances = cmis_cdb_instances_get(map); + + printf("\t%-41s : %u\n", "CDB instances", cdb_instances); +} + +static void cmis_show_cdb_mode(const struct cmis_memory_map *map) +{ + __u8 mode = map->page_01h[CMIS_CDB_ADVER_OFFSET] & + CMIS_CDB_ADVER_MODE_MASK; + + printf("\t%-41s : %s\n", "CDB background mode", + mode ? "Supported" : "Not supported"); +} + +static void cmis_show_cdb_epl_pages(const struct cmis_memory_map *map) +{ + __u8 epl_pages = map->page_01h[CMIS_CDB_ADVER_OFFSET] & + CMIS_CDB_ADVER_EPL_MASK; + + printf("\t%-41s : %u\n", "CDB EPL pages", epl_pages); +} + +static void cmis_show_cdb_rw_len(const struct cmis_memory_map *map) +{ + __u16 rw_len = map->page_01h[CMIS_CDB_ADVER_RW_LEN_OFFSET]; + + /* Maximum read / write length for CDB EPL pages and the LPL page in + * units of 8 bytes, in addition to the minimum 8 bytes. + */ + rw_len = (rw_len + 1) * 8; + printf("\t%-41s : %u\n", "CDB Maximum EPL RW length", rw_len); + printf("\t%-41s : %u\n", "CDB Maximum LPL RW length", + rw_len > CMIS_PAGE_SIZE ? CMIS_PAGE_SIZE : rw_len); +} + +static void cmis_show_cdb_trigger(const struct cmis_memory_map *map) +{ + __u8 trigger = map->page_01h[CMIS_CDB_ADVER_TRIGGER_OFFSET] & + CMIS_CDB_ADVER_TRIGGER_MASK; + + /* Whether a CDB command can be triggered in a single write to the LPL + * page, or by multiple writes ending with the writing of the CDB + * Command Code (CMDID). + */ + printf("\t%-41s : %s\n", "CDB trigger method", + trigger ? "Single write" : "Multiple writes"); +} + +/* Print CDB messaging support advertisement. Relevant documents: + * [1] CMIS Rev. 5, page 133, section 8.4.11 + */ +static void cmis_show_cdb_adver(const struct cmis_memory_map *map) +{ + if (!map->page_01h || !cmis_cdb_is_supported(map)) + return; + + cmis_show_cdb_instances(map); + cmis_show_cdb_mode(map); + cmis_show_cdb_epl_pages(map); + cmis_show_cdb_rw_len(map); + cmis_show_cdb_trigger(map); +} + static void cmis_show_all_common(const struct cmis_memory_map *map) { cmis_show_identifier(map); @@ -945,6 +1024,7 @@ static void cmis_show_all_common(const struct cmis_memory_map *map) cmis_show_mod_lvl_controls(map); cmis_show_dom(map); cmis_show_fw_version(map); + cmis_show_cdb_adver(map); } static void cmis_memory_map_init_buf(struct cmis_memory_map *map, diff --git a/cmis.h b/cmis.h index 3015c54..cee2a38 100644 --- a/cmis.h +++ b/cmis.h @@ -191,6 +191,17 @@ #define CMIS_SIG_INTEG_TX_OFFSET 0xA1 #define CMIS_SIG_INTEG_RX_OFFSET 0xA2 +/* CDB Messaging Support Advertisement */ +#define CMIS_CDB_ADVER_OFFSET 0xA3 +#define CMIS_CDB_ADVER_INSTANCES_MASK 0xC0 +#define CMIS_CDB_ADVER_MODE_MASK 0x20 +#define CMIS_CDB_ADVER_EPL_MASK 0x0F + +#define CMIS_CDB_ADVER_RW_LEN_OFFSET 0xA4 + +#define CMIS_CDB_ADVER_TRIGGER_OFFSET 0xA5 +#define CMIS_CDB_ADVER_TRIGGER_MASK 0x80 + /*----------------------------------------------------------------------- * Upper Memory Page 0x02: Optional Page that informs about module-defined * thresholds for module-level and lane-specific threshold crossing monitors.