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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Rahul Rameshbabu , Tariq Toukan Subject: [PATCH net 6/8] net/mlx5e: Require mlx5 tc classifier action support for IPsec prio capability Date: Tue, 30 Jul 2024 09:16:35 +0300 Message-ID: <20240730061638.1831002-7-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240730061638.1831002-1-tariqt@nvidia.com> References: <20240730061638.1831002-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D8:EE_|SA1PR12MB7200:EE_ X-MS-Office365-Filtering-Correlation-Id: c47fc560-901c-4ed0-d40a-08dcb05f76ac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: LZ6xpspupe+XXnpDT6LfICWnY3yj10krN5dhamReiOCskFssJdKdiOxSkuKc4xj8wi5FV4Y4Vwjl+B1Jyori0UD5eJTUax5GLeD/0gDoXgDXRgpza9er6EVjqeakg3D9DmGoEI3eY6v87Ib+g7zeyXjNIhnKWezXbZDHfaCXFK/97G4Fh3Mo1MN1ToNLhCaokRZeeQxBoIhnsNP3MCbqBkiKmjBhlw9L1cGUaavZsRemBNaV7N0z+Xeukh+/ckdJsUm2kgxIm9ojhToQp3qfPGLmo7m8kWfF8C2saYLjr6lpqdAcvxTtXOpg7PA7cC6U21vBYVFZYB1Ku+dhf/dbaTeTZEZGIqp7dBzVsNz7tUWLdhbI3ccm5fFmTuebQoV4MIyo/Vgn3Y6e9UTtorVGbnUV2QVWNHrNyUKcDkBu0qMGQgVLWRiHEorf5/8NOhjQ9IdcuS+VY3tqHilRSA27VUsmDfTPJG0os1vq7Z4T3o5r8o244dHFe+lrIShk28pPUxYeDTPPYcP1NAXAiEOC7Ho99HLxgPkwIO6b2G3Xct5B5g/u0NKI+i04dKuRTutMFT7oHVCAnm/3vkFmShAWV0NN+k1CWmhG/GFgxga0iKxEa+RbZ3cjL8WNQ6zVLKUpTT8jWbguJWhCZNeKa4hsVhFZVHTzXKAzvpdwjGaQxRT2ZS8sUKxyQaSbrPK9DSzdcVm5sPAQsGcaIumZJhkxqfSRryNdhag15XZhAfKzdU2KeS1dxU/SGw7DhpZ0dLOvEgFTmR8PSTDn7L1dBw1E3bAO/eYVQlOcjkzzWCtLgyA8KBtKSWRYPSGRMMZP1MaKHEBD3fuP5Wnj4yKLLK/iEEwB/c5TxqolPtocq7LNbZI5k0Ekm74gwxB+VhsvOT62AXW28ZzBPsWjGVs/xpNsXTRwop1+ry1ij1YXg8gYxnJwKidReHbHyGGHUOrKglzjaPptrf8R9R/g4jk4b1pMdaLrp58d9tSDwshU/zm78GGu+BP+M3AYE6P6oZLDEp8nYa2xDUp+y+PycS8W+m/RmArjq5usUPuA/0zQC6IRqZS/Lu9Cp6c1hFjgkjNxgrnqnNUJQMTBTsaWKVlnVjOWInYQCY5LxvljeZJNkYxt7J4j8B1fC56vAJACFqpI2KjUBre/j2xnx/2nsWReeLT3jG02lb4rPz+A+Vh04Ij0LZniU32yQ2q4QNa9AUUZcZ2MR6TAy6l8dUJOKBMiVTN/yrHdaY6fSdtewfF3FBOxtuf9LktarVNFvvfzJsg9AWKiCXN83X+oIjnZstRpo2KqmFY66T+tJDjgOXU6RotVm9RgCEXVK1FoECdwjrg1J3gaRa/t8fUQAVQ43OwmVi+cVBTMPSrLtPXA5DapfBswVcuLjS6W+auKQCVdcM96I6ZHodKBv6uFFVtLe36bg+vdF4OZB2uAURvVQxjPNPJmx78qYXwueeHkc3y+Zw2Kdl9p X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 06:18:43.7624 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c47fc560-901c-4ed0-d40a-08dcb05f76ac X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7200 X-Patchwork-Delegate: kuba@kernel.org From: Rahul Rameshbabu Require mlx5 classifier action support when creating IPSec chains in offload path. MLX5_IPSEC_CAP_PRIO should only be set if CONFIG_MLX5_CLS_ACT is enabled. If CONFIG_MLX5_CLS_ACT=n and MLX5_IPSEC_CAP_PRIO is set, configuring IPsec offload will fail due to the mlxx5 ipsec chain rules failing to be created due to lack of classifier action support. Fixes: fa5aa2f89073 ("net/mlx5e: Use chains for IPsec policy priority offload") Signed-off-by: Rahul Rameshbabu Reviewed-by: Leon Romanovsky Signed-off-by: Tariq Toukan Reviewed-by: Wojciech Drewek --- .../ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c index 6e00afe4671b..797db853de36 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c @@ -51,9 +51,10 @@ u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev) MLX5_CAP_FLOWTABLE_NIC_RX(mdev, decap)) caps |= MLX5_IPSEC_CAP_PACKET_OFFLOAD; - if ((MLX5_CAP_FLOWTABLE_NIC_TX(mdev, ignore_flow_level) && - MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ignore_flow_level)) || - MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, ignore_flow_level)) + if (IS_ENABLED(CONFIG_MLX5_CLS_ACT) && + ((MLX5_CAP_FLOWTABLE_NIC_TX(mdev, ignore_flow_level) && + MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ignore_flow_level)) || + MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, ignore_flow_level))) caps |= MLX5_IPSEC_CAP_PRIO; if (MLX5_CAP_FLOWTABLE_NIC_TX(mdev,