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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Dragos Tatulea , Tariq Toukan Subject: [PATCH net 2/4] net/mlx5e: SHAMPO, Release in progress headers Date: Thu, 15 Aug 2024 10:16:09 +0300 Message-ID: <20240815071611.2211873-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240815071611.2211873-1-tariqt@nvidia.com> References: <20240815071611.2211873-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992C:EE_|DM6PR12MB4154:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a67dbe1-1bda-4db2-1cf4-08dcbcfa7e84 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: texUlLMeTL+CEI+RxbG90hgvBdoLy8uJqPD767zpWrmZGOIDQ5dlqH4UPida0eivacAyuDwUKPZwhi4fyyMAdrQjEJI702jBxntdEDWdCOEXRRG6PBaR85eiqvZ0eF6y2G4Ka8vl7OsBe8onoXS7zISEdmofq2A/MfkTwleFrL4NFdD5l3l3R/3jBkW89kPiVobdLNNQ+/4pQh7Kt0zEIQFoD3T6O06SfqMlnNrYyewQSkCWSesojDfFXlYgPWn6FwcUfSiOaoox1+/yMSPg20fDrmNFu+TTdUIQdJRxkfNbrfaKRmoM7u2wGU3bsKnqqg5Ysd+WI5SGZWLdaqU71HJe5q/efzu0vwhKrRHn5pHuzcFncabvIQRqm5jpNSMW1VddgFNqaNT9bUVj73jD3zISgSEsuLL1KG67L3ddDX2XQOWp64XTq56kbsW1Asa4v5HbbekZj27H3LgrqMqiLoR8wfgc6RjYBsgAoNSMJNr2Yy+DHx2KaNCX/JBSRbK9z0ewjVZqJxxGbA5f8kcRCSBPLN+kvg1Ze1dwU0MVKIx22A3MqEIWcEigYY44YHdyD+c40Nc6HGWJ/9+OpmTp4PqR8j8zo+spyup7p69lg2hJkqs1XuJuVngacmjk5XuXtGl+mz3wMhYSEHLXObox7WLrNs1wppvjphywuKOpycAg710F+r1ijRAsq8HsqtNL6ir6zjMNgLBTCnGBdDUhEgJvw8HuAh96yxxNKfcuowaaH3Of7GmTyK0pX+kMloK6UT7s6o9sRjd+IycDlf3iRlpCp2GVsO7uaxbW71+FQRl8YxGP016TDFReH6HVGVSexsKY1DFMRpYzTLeITUsPEslWZ5is8oM/VyqVGSgZjtA6i07yPUWBurK42PabgS0iWJICIwZd4+L3Qu5xbenJkCNBuEPU2RxEsY0HeJ5xh1qvdh4asn7mYG1u0Z7/sPWzA6TgrLz43FUYy+X9OY0t0e/4PdnURjjHhLBj8F+iwp8dX8XtJSAD2k/wV2cVEIl5DXlMf2pr3GxOtNuWD1I5SkBlb72GqFDTtoAn2sRI8yjSp8MhKDP08KxH3+dtiIms1Q7/hMfxf7jboUUs/j9n2uNDnxdesT+QI1uxe9gj8GCvjvc45Ii0rHKdbzHJHri57IyMl5I5YoKyDulKnI2v9yCRXaEee23TUBr8mNsWi1CBU5gYYg+iDOYQa5ENWy0kJ+uBq8obS2pMrzNSZdML/egLIO+O3OfXSXgn/rCrb49YCh/O6LFs4c55W1H4agCGAo+sV8RXPoh4SeZvGFH7WDK+65UboHdhWqW705UWREErAM+bLK08gcTw2mqsCEdZr+CaqPeZnTSzMPnWl+f+N5zbjE6aBp/qe5o+2EBaK2HyyM0d3Z+fKsOJevryGmLCYz3u5yqdiOF6sAoJMjSAlBPILguY1NmRetIqymi3kgs41M2qAP0lkzyxlHuLn5PI X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2024 07:18:42.8326 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a67dbe1-1bda-4db2-1cf4-08dcbcfa7e84 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4154 X-Patchwork-Delegate: kuba@kernel.org From: Dragos Tatulea The change in the fixes tag cleaned up too much: it removed the part that was releasing header pages that were posted via UMR but haven't been acknowledged yet on the ICOSQ. This patch corrects this omission by setting the bits between pi and ci to on when shutting down a queue with SHAMPO. To be consistent with the Striding RQ code, this action is done in mlx5e_free_rx_missing_descs(). Fixes: e839ac9a89cb ("net/mlx5e: SHAMPO, Simplify header page release in teardown") Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 + .../net/ethernet/mellanox/mlx5/core/en_main.c | 8 ++++++ .../net/ethernet/mellanox/mlx5/core/en_rx.c | 25 +++++++++++-------- 3 files changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index bb5da42edc23..d9e241423bc5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -998,6 +998,7 @@ void mlx5e_build_ptys2ethtool_map(void); bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift, enum mlx5e_mpwrq_umr_mode umr_mode); +void mlx5e_shampo_fill_umr(struct mlx5e_rq *rq, int len); void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq); void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 5df904639b0c..583fa24a7ae9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -1236,6 +1236,14 @@ void mlx5e_free_rx_missing_descs(struct mlx5e_rq *rq) rq->mpwqe.actual_wq_head = wq->head; rq->mpwqe.umr_in_progress = 0; rq->mpwqe.umr_completed = 0; + + if (test_bit(MLX5E_RQ_STATE_SHAMPO, &rq->state)) { + struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo; + u16 len; + + len = (shampo->pi - shampo->ci) & shampo->hd_per_wq; + mlx5e_shampo_fill_umr(rq, len); + } } void mlx5e_free_rx_descs(struct mlx5e_rq *rq) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c index 23aa555ca0ae..de9d01036c28 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -963,26 +963,31 @@ void mlx5e_free_icosq_descs(struct mlx5e_icosq *sq) sq->cc = sqcc; } -static void mlx5e_handle_shampo_hd_umr(struct mlx5e_shampo_umr umr, - struct mlx5e_icosq *sq) +void mlx5e_shampo_fill_umr(struct mlx5e_rq *rq, int len) { - struct mlx5e_channel *c = container_of(sq, struct mlx5e_channel, icosq); - struct mlx5e_shampo_hd *shampo; - /* assume 1:1 relationship between RQ and icosq */ - struct mlx5e_rq *rq = &c->rq; - int end, from, len = umr.len; + struct mlx5e_shampo_hd *shampo = rq->mpwqe.shampo; + int end, from, full_len = len; - shampo = rq->mpwqe.shampo; end = shampo->hd_per_wq; from = shampo->ci; - if (from + len > shampo->hd_per_wq) { + if (from + len > end) { len -= end - from; bitmap_set(shampo->bitmap, from, end - from); from = 0; } bitmap_set(shampo->bitmap, from, len); - shampo->ci = (shampo->ci + umr.len) & (shampo->hd_per_wq - 1); + shampo->ci = (shampo->ci + full_len) & (shampo->hd_per_wq - 1); +} + +static void mlx5e_handle_shampo_hd_umr(struct mlx5e_shampo_umr umr, + struct mlx5e_icosq *sq) +{ + struct mlx5e_channel *c = container_of(sq, struct mlx5e_channel, icosq); + /* assume 1:1 relationship between RQ and icosq */ + struct mlx5e_rq *rq = &c->rq; + + mlx5e_shampo_fill_umr(rq, umr.len); } int mlx5e_poll_ico_cq(struct mlx5e_cq *cq)