From patchwork Thu Aug 29 11:28:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karol Kolacinski X-Patchwork-Id: 13783045 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B32F191F90 for ; Thu, 29 Aug 2024 11:33:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724931200; cv=none; b=T88DgY7jRrz3uDhFSv64boG407SYdkPpz2LyAGpGy1icSPzFgqpFAQJEI1jJLX9kNjweJsi5UiQZzjsL9y1ErW7744iJnO9PiTV31lIjDeBorxSJda3USMXSQVEvoOzabywF/ycu2KArsJS24e9ynXQj9pR5Strh5yW5ulRkLMw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724931200; c=relaxed/simple; bh=p7xgIQH0bb8bKwQrlGLYcFI7oXY+3QHoY5PQPeXaia8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=i7FP+LQOrwpxw+YTtawxsJiw0eIalmMN5ZN5eGS+2AADTmZD7VV73Zt2VnThSMXm4b+AqIh4ZQRhR759ROezWFVVZU0cJ4PNnB6ZPeosWLrhHkZnFqXGZap23ulr1I6jqJEAos5m1pXWQ0AlL0fuxQ5TszNZlduGAPo0BjlEuVU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NcMkngPc; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NcMkngPc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724931199; x=1756467199; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p7xgIQH0bb8bKwQrlGLYcFI7oXY+3QHoY5PQPeXaia8=; b=NcMkngPczHC65xN+qRcsQq21tVjKX0j/lGNpT2LmF7PfKlYax8oamkxo CSy4qP9gpmxVjkfq4GYYFR27A654tNX+2IFA5rH2zRLWSTQ3tYMxo6XSP xv/9wDkIL1eyn9bhPMPDWvJlH9uPRuM4u9NclcwJDj4Nz/X1iB/YV5SB/ lPqFn06d9PtANWO2uqTL6epjt+HORQbVMBJVSB2kSUE6ep/GlP/LZavL8 xp3kwv3ptSd7h181gdf49VB0QfrpJrtMYlL8zoP3VDTWjRmNaQ6qu1g7I AEq4Yp0Mm6AIqZfgHjub0IYCLJVVSOEme81bmDnQTOZ4YprD4lv4AKE6Q A==; X-CSE-ConnectionGUID: pCcnLW3bRaaKBV4WuuFC4Q== X-CSE-MsgGUID: SQMH5g8rR2qhFxHLUnpVeA== X-IronPort-AV: E=McAfee;i="6700,10204,11178"; a="23677896" X-IronPort-AV: E=Sophos;i="6.10,185,1719903600"; d="scan'208";a="23677896" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2024 04:33:18 -0700 X-CSE-ConnectionGUID: SBja+CndSGic8cOqGCQg6g== X-CSE-MsgGUID: F1uRUSsoSVum0eHkBXrF6g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,185,1719903600"; d="scan'208";a="63230630" Received: from kkolacin-desk1.igk.intel.com ([10.217.160.108]) by fmviesa007.fm.intel.com with ESMTP; 29 Aug 2024 04:33:17 -0700 From: Karol Kolacinski To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, Sergey Temerkhanov , Arkadiusz Kubalewski , Karol Kolacinski Subject: [PATCH v3 iwl-next 7/7] ice: Enable 1PPS out from CGU for E825C products Date: Thu, 29 Aug 2024 13:28:14 +0200 Message-ID: <20240829113257.1023835-16-karol.kolacinski@intel.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240829113257.1023835-9-karol.kolacinski@intel.com> References: <20240829113257.1023835-9-karol.kolacinski@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Sergey Temerkhanov Implement configuring 1PPS signal output from CGU. Use maximal amplitude because Linux PTP pin API does not have any way for user to set signal level. This change is necessary for E825C products to properly output any signal from 1PPS pin. Reviewed-by: Arkadiusz Kubalewski Signed-off-by: Sergey Temerkhanov Co-developed-by: Karol Kolacinski Signed-off-by: Karol Kolacinski --- V1 -> V2: Added return value description, renamed the function and enable parameter. Reworded commit message. drivers/net/ethernet/intel/ice/ice_ptp.c | 10 +++++++++ drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 23 +++++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 1 + 3 files changed, 34 insertions(+) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index a35ffc31f316..e275201dff36 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -4,6 +4,7 @@ #include "ice.h" #include "ice_lib.h" #include "ice_trace.h" +#include "ice_cgu_regs.h" static const char ice_pin_names[][64] = { "SDP0", @@ -1709,6 +1710,15 @@ static int ice_ptp_write_perout(struct ice_hw *hw, unsigned int chan, /* 0. Reset mode & out_en in AUX_OUT */ wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), 0); + if (ice_is_e825c(hw)) { + int err; + + /* Enable/disable CGU 1PPS output for E825C */ + err = ice_cgu_cfg_pps_out(hw, !!period); + if (err) + return err; + } + /* 1. Write perout with half of required period value. * HW toggles output when source clock hits the TGT and then adds * GLTSYN_CLKO value to the target, so it ends up with 50% duty cycle. diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 07ecf2a86742..6dff422b7f4e 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -661,6 +661,29 @@ static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw, return 0; } +#define ICE_ONE_PPS_OUT_AMP_MAX 3 + +/** + * ice_cgu_cfg_pps_out - Configure 1PPS output from CGU + * @hw: pointer to the HW struct + * @enable: true to enable 1PPS output, false to disable it + * + * Return: 0 on success, other negative error code when CGU read/write failed + */ +int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable) +{ + union nac_cgu_dword9 dw9; + int err; + + err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); + if (err) + return err; + + dw9.one_pps_out_en = enable; + dw9.one_pps_out_amp = enable * ICE_ONE_PPS_OUT_AMP_MAX; + return ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); +} + /** * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits * @hw: pointer to the HW struct diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index ff98f76969e3..fc946fcd28b9 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -331,6 +331,7 @@ extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD]; /* Device agnostic functions */ u8 ice_get_ptp_src_clock_index(struct ice_hw *hw); +int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable); bool ice_ptp_lock(struct ice_hw *hw); void ice_ptp_unlock(struct ice_hw *hw); void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd);