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Sat, 7 Sep 2024 03:19:41 -0500 Received: from xcbalucerop41x.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39 via Frontend Transport; Sat, 7 Sep 2024 03:19:40 -0500 From: To: , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v3 12/20] efx: use acquire_endpoint when looking for free HPA Date: Sat, 7 Sep 2024 09:18:28 +0100 Message-ID: <20240907081836.5801-13-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240907081836.5801-1-alejandro.lucero-palau@amd.com> References: <20240907081836.5801-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709B:EE_|SN7PR12MB7369:EE_ X-MS-Office365-Filtering-Correlation-Id: fb706f70-3c4c-4c12-07cf-08dccf15d358 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2024 08:19:42.5698 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb706f70-3c4c-4c12-07cf-08dccf15d358 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7369 X-Patchwork-Delegate: kuba@kernel.org From: Alejandro Lucero Asking for availbale HPA space is the previous step to try to obtain an HPA range suitable to accel driver purposes. Add this call to efx cxl initialization and use acquire_endpoint for avoiding potential races with cxl port creation. Signed-off-by: Alejandro Lucero --- drivers/net/ethernet/sfc/efx.c | 8 +++++++- drivers/net/ethernet/sfc/efx_cxl.c | 32 ++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/sfc/efx.c b/drivers/net/ethernet/sfc/efx.c index 3a7406aa950c..08a2f527df16 100644 --- a/drivers/net/ethernet/sfc/efx.c +++ b/drivers/net/ethernet/sfc/efx.c @@ -1117,10 +1117,16 @@ static int efx_pci_probe(struct pci_dev *pci_dev, * used for PIO buffers. If there is no CXL support, or initialization * fails, efx_cxl_pio_initialised wll be false and legacy PIO buffers * defined at specific PCI BAR regions will be used. + * + * The only error to handle is -EPROBE_DEFER happening if the root port + * is not there yet. */ rc = efx_cxl_init(efx); - if (rc) + if (rc) { + if (rc == -EPROBE_DEFER) + goto fail2; pci_err(pci_dev, "CXL initialization failed with error %d\n", rc); + } rc = efx_pci_probe_post_io(efx); if (rc) { diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c index 899bc823a212..826759caa552 100644 --- a/drivers/net/ethernet/sfc/efx_cxl.c +++ b/drivers/net/ethernet/sfc/efx_cxl.c @@ -23,6 +23,7 @@ int efx_cxl_init(struct efx_nic *efx) struct pci_dev *pci_dev = efx->pci_dev; struct efx_cxl *cxl; struct resource res; + resource_size_t max; u16 dvsec; int rc; @@ -90,7 +91,38 @@ int efx_cxl_init(struct efx_nic *efx) goto err; } + cxl->endpoint = cxl_acquire_endpoint(cxl->cxlmd); + if (IS_ERR(cxl->endpoint)) { + rc = PTR_ERR(cxl->endpoint); + if (rc != -EPROBE_DEFER) { + pci_err(pci_dev, "CXL accel acquire endpoint failed"); + goto err; + } + } + + cxl->cxlrd = cxl_get_hpa_freespace(cxl->endpoint, + CXL_DECODER_F_RAM | CXL_DECODER_F_TYPE2, + &max); + + if (IS_ERR(cxl->cxlrd)) { + pci_err(pci_dev, "cxl_get_hpa_freespace failed\n"); + rc = PTR_ERR(cxl->cxlrd); + goto err_release; + } + + if (max < EFX_CTPIO_BUFFER_SIZE) { + pci_err(pci_dev, "%s: no enough free HPA space %llu < %u\n", + __func__, max, EFX_CTPIO_BUFFER_SIZE); + rc = -ENOSPC; + goto err; + } + + cxl_release_endpoint(cxl->cxlmd, cxl->endpoint); + return 0; + +err_release: + cxl_release_endpoint(cxl->cxlmd, cxl->endpoint); err: kfree(cxl->cxlds); kfree(cxl);