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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2024 08:19:28.5790 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ae98a0fb-2cb8-4ebf-5c29-08dccf15cb08 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EA.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR12MB8567 X-Patchwork-Delegate: kuba@kernel.org From: Alejandro Lucero Create a new function for a type2 device initialising cxl_dev_state struct regarding cxl regs setup and mapping. Signed-off-by: Alejandro Lucero --- drivers/cxl/core/pci.c | 30 ++++++++++++++++++++++++++++++ drivers/net/ethernet/sfc/efx_cxl.c | 6 ++++++ include/linux/cxl/cxl.h | 2 ++ 3 files changed, 38 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index bf57f081ef8f..9afcdd643866 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1142,6 +1142,36 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, } EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL); +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) +{ + struct cxl_register_map map; + int rc; + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, + &cxlds->capabilities); + if (!rc) { + rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); + if (rc) + return rc; + } + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, + &cxlds->reg_map, &cxlds->capabilities); + if (rc) + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); + + if (cxlds->capabilities & BIT(CXL_CM_CAP_CAP_ID_RAS)) { + rc = cxl_map_component_regs(&cxlds->reg_map, + &cxlds->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS)); + if (rc) + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); + } + + return rc; +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, CXL); + bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, u32 expected_caps, u32 *current_caps) { diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c index bba36cbbab22..fee143e94c1f 100644 --- a/drivers/net/ethernet/sfc/efx_cxl.c +++ b/drivers/net/ethernet/sfc/efx_cxl.c @@ -66,6 +66,12 @@ int efx_cxl_init(struct efx_nic *efx) goto err; } + rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds); + if (rc) { + pci_err(pci_dev, "CXL accel setup regs failed"); + goto err; + } + return 0; err: kfree(cxl->cxlds); diff --git a/include/linux/cxl/cxl.h b/include/linux/cxl/cxl.h index 4a57bf60403d..f2dcba6cdc22 100644 --- a/include/linux/cxl/cxl.h +++ b/include/linux/cxl/cxl.h @@ -5,6 +5,7 @@ #define __CXL_H #include +#include enum cxl_resource { CXL_ACCEL_RES_DPA, @@ -50,4 +51,5 @@ int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res, enum cxl_resource); bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, u32 expected_caps, u32 *current_caps); +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds); #endif