Message ID | 20240911201757.1505453-10-saeed@kernel.org (mailing list archive) |
---|---|
State | Accepted |
Commit | 9947204cdad97d22d171039019a4aad4d6899cdd |
Delegated to: | Netdev Maintainers |
Headers | show |
Series | [net-next,01/15] net/mlx5: HWS, updated API functions comments to kernel doc | expand |
On 9/11/2024 1:17 PM, Saeed Mahameed wrote: > From: Moshe Shemesh <moshe@nvidia.com> > > New devices with new FW can support sync reset for firmware activate > using hot reset. Add capability for supporting it and add MFRL field to > query from FW which type of PCI reset method to use while handling sync > reset events. > > Signed-off-by: Moshe Shemesh <moshe@nvidia.com> > Signed-off-by: Saeed Mahameed <saeedm@nvidia.com> > --- Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index b6f8e3834bd3..542da2b066d1 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1855,7 +1855,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_328[0x2]; u8 relaxed_ordering_read[0x1]; u8 log_max_pd[0x5]; - u8 reserved_at_330[0x6]; + u8 reserved_at_330[0x5]; + u8 pcie_reset_using_hotreset_method[0x1]; u8 pci_sync_for_fw_update_with_driver_unload[0x1]; u8 vnic_env_cnt_steering_fail[0x1]; u8 vport_counter_local_loopback[0x1]; @@ -11180,6 +11181,11 @@ struct mlx5_ifc_mcda_reg_bits { u8 data[][0x20]; }; +enum { + MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0, + MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1, +}; + enum { MLX5_MFRL_REG_RESET_STATE_IDLE = 0, MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, @@ -11207,7 +11213,8 @@ struct mlx5_ifc_mfrl_reg_bits { u8 pci_sync_for_fw_update_start[0x1]; u8 pci_sync_for_fw_update_resp[0x2]; u8 rst_type_sel[0x3]; - u8 reserved_at_28[0x4]; + u8 pci_reset_req_method[0x3]; + u8 reserved_at_2b[0x1]; u8 reset_state[0x4]; u8 reset_type[0x8]; u8 reset_level[0x8];