From patchwork Fri Oct 4 10:24:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2t5TGFrZSBIdWFuZyAo6buD5ZWf5r6kKQ==?= X-Patchwork-Id: 13822127 X-Patchwork-Delegate: kuba@kernel.org Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C892156236; Fri, 4 Oct 2024 10:31:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037888; cv=none; b=OvNg+hmEus2vzDm4ubra8JEExFqulHBZyvfy7v5QektsOOzY33Y5aP6xlqArruqlgfvu2DZ98zUfxGfdvqLf3SQDYJazse8HnVuiHYY/qA0XLEhWc2JcUwph+0uHe702/0lXYjVfe7qQXBo2oJ4Yj8ihgvRJqiuzr+SBIMkjEtU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037888; c=relaxed/simple; bh=gRNq3+UJJYYEUtNzlLInxG6mCzdHRZ0fvq6cPdab8p4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ei04jiKYUVYCK5PeF3IPsZPhMQqbiQYF/pvYqu1cC2izPbswxGnbn3QX6r6cZjqFHRo/pEkA6wkIDJqivP3SAEB9cRdv3Hfx1QGAYV6z/OzcRaETDLKxzdLUqh4QlLaIQT4/re92aL+iYVx/tR52XJvJ57MB3hHjP7DWRRiR3CA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=iHpayIEX; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="iHpayIEX" X-UUID: cbeb0fd0823b11ef8b96093e013ec31c-20241004 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=kFjaXTcU9JT7uWD+4LXrSs69ImCde9P7Qo4WUuG3Z9o=; b=iHpayIEX5RKF36xpMPr358uzY0o2suA2LU50e52YyVvUpfYEdnfvCN2isndz2FyN1NX0mfOudB3JqHq9Hleq2DlPF+m2R99YGX8sUffL83kD6SbBg03J5OdinONdoBJYgotYP97ikdJeWD4l+djfUqZO4a7TGAoBCuf9d2l6kek=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:b8e5e741-15a3-4edf-b887-82163822b156,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6dc6a47,CLOUDID:70214a26-5902-4533-af4f-d0904aa89b3c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:1,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: cbeb0fd0823b11ef8b96093e013ec31c-20241004 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 144039363; Fri, 04 Oct 2024 18:31:20 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 4 Oct 2024 18:31:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 4 Oct 2024 18:31:19 +0800 From: Sky Huang To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , , , , CC: Steven Liu , SkyLake.Huang Subject: [PATCH net-next 8/9] net: phy: mediatek: Change mtk-ge-soc.c line wrapping Date: Fri, 4 Oct 2024 18:24:12 +0800 Message-ID: <20241004102413.5838-9-SkyLake.Huang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241004102413.5838-1-SkyLake.Huang@mediatek.com> References: <20241004102413.5838-1-SkyLake.Huang@mediatek.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N X-Patchwork-Delegate: kuba@kernel.org From: "SkyLake.Huang" This patch shrinks mtk-ge-soc.c line wrapping to 80 characters. Signed-off-by: SkyLake.Huang --- drivers/net/phy/mediatek/mtk-ge-soc.c | 67 +++++++++++++++++---------- 1 file changed, 42 insertions(+), 25 deletions(-) diff --git a/drivers/net/phy/mediatek/mtk-ge-soc.c b/drivers/net/phy/mediatek/mtk-ge-soc.c index 26c2183..cb6838b 100644 --- a/drivers/net/phy/mediatek/mtk-ge-soc.c +++ b/drivers/net/phy/mediatek/mtk-ge-soc.c @@ -295,7 +295,8 @@ static int cal_cycle(struct phy_device *phydev, int devad, ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_CLK, reg_val, reg_val & MTK_PHY_DA_CAL_CLK, 500, - ANALOG_INTERNAL_OPERATION_MAX_US, false); + ANALOG_INTERNAL_OPERATION_MAX_US, + false); if (ret) { phydev_err(phydev, "Calibration cycle timeout\n"); return ret; @@ -304,7 +305,7 @@ static int cal_cycle(struct phy_device *phydev, int devad, phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, MTK_PHY_DA_CALIN_FLAG); ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> - MTK_PHY_AD_CAL_COMP_OUT_SHIFT; + MTK_PHY_AD_CAL_COMP_OUT_SHIFT; phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); return ret; @@ -394,38 +395,46 @@ static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) } phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, - MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); + MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, + (buf[0] + bias[0]) << 10); phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, - MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); + MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, + (buf[0] + bias[2]) << 10); phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, - MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); + MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, + (buf[1] + bias[4]) << 8); phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, - MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); + MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, + (buf[1] + bias[6]) << 8); phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, - MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); + MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, + (buf[2] + bias[8]) << 8); phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, - MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); + MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, + (buf[2] + bias[10]) << 8); phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, - MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); + MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, + (buf[3] + bias[12]) << 8); phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, - MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); + MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, + (buf[3] + bias[14]) << 8); phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); @@ -616,7 +625,8 @@ static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) goto restore; /* We calibrate TX-VCM in different logic. Check upper index and then - * lower index. If this calibration is valid, apply lower index's result. + * lower index. If this calibration is valid, apply lower index's + * result. */ ret = upper_ret - lower_ret; if (ret == 1) { @@ -645,7 +655,8 @@ static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && lower_ret == 0) { ret = 0; - phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", + phydev_warn(phydev, + "TX-VCM SW cal result at high margin 0x%x\n", upper_idx); } else { ret = -EINVAL; @@ -749,7 +760,8 @@ static void mt7981_phy_finetune(struct phy_device *phydev) /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, - MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, + MTK_PHY_TR_OPEN_LOOP_EN_MASK | + MTK_PHY_LPF_X_AVERAGE_MASK, BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); /* rg_tr_lpf_cnt_val = 512 */ @@ -818,7 +830,8 @@ static void mt7988_phy_finetune(struct phy_device *phydev) /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, - MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, + MTK_PHY_TR_OPEN_LOOP_EN_MASK | + MTK_PHY_LPF_X_AVERAGE_MASK, BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); /* rg_tr_lpf_cnt_val = 1023 */ @@ -930,7 +943,8 @@ static void mt798x_phy_eee(struct phy_device *phydev) phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); - __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, + __phy_modify(phydev, MTK_PHY_LPI_REG_14, + MTK_PHY_LPI_WAKE_TIMER_1000_MASK, FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, @@ -940,7 +954,8 @@ static void mt798x_phy_eee(struct phy_device *phydev) phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, - FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); + FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, + 0xff)); } static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, @@ -1119,14 +1134,15 @@ static int mt798x_phy_led_brightness_set(struct phy_device *phydev, MTK_GPHY_LED_ON_MASK, (value != LED_OFF)); } -static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) | - BIT(TRIGGER_NETDEV_HALF_DUPLEX) | - BIT(TRIGGER_NETDEV_LINK) | - BIT(TRIGGER_NETDEV_LINK_10) | - BIT(TRIGGER_NETDEV_LINK_100) | - BIT(TRIGGER_NETDEV_LINK_1000) | - BIT(TRIGGER_NETDEV_RX) | - BIT(TRIGGER_NETDEV_TX)); +static const unsigned long supported_triggers = + (BIT(TRIGGER_NETDEV_FULL_DUPLEX) | + BIT(TRIGGER_NETDEV_HALF_DUPLEX) | + BIT(TRIGGER_NETDEV_LINK) | + BIT(TRIGGER_NETDEV_LINK_10) | + BIT(TRIGGER_NETDEV_LINK_100) | + BIT(TRIGGER_NETDEV_LINK_1000) | + BIT(TRIGGER_NETDEV_RX) | + BIT(TRIGGER_NETDEV_TX)); static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, unsigned long rules) @@ -1189,7 +1205,8 @@ static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev) /* Only now setup pinctrl to avoid bogus blinking */ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); if (IS_ERR(pinctrl)) - dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED pinctrl\n"); + dev_err(&phydev->mdio.bus->dev, + "Failed to setup PHY LED pinctrl\n"); return 0; }