Message ID | 20241004152419.79465-2-francesco@dolcini.it (mailing list archive) |
---|---|
State | Accepted |
Commit | 1aa772be0444a2bd06957f6d31865e80e6ae4244 |
Delegated to: | Netdev Maintainers |
Headers | show |
Series | net: fec: add PPS channel configuration | expand |
On Fri, Oct 04, 2024 at 05:24:17PM +0200, Francesco Dolcini wrote: > From: Francesco Dolcini <francesco.dolcini@toradex.com> > > Add fsl,pps-channel property to select where to connect the PPS signal. > This depends on the internal SoC routing and on the board, for example > on the i.MX8 SoC it can be connected to an external pin (using channel 1) > or to internal eDMA as DMA request (channel 0). > > Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Acked-by: Conor Dooley <conor.dooley@microchip.com>
diff --git a/Documentation/devicetree/bindings/net/fsl,fec.yaml b/Documentation/devicetree/bindings/net/fsl,fec.yaml index 5536c06139ca..24e863fdbdab 100644 --- a/Documentation/devicetree/bindings/net/fsl,fec.yaml +++ b/Documentation/devicetree/bindings/net/fsl,fec.yaml @@ -183,6 +183,13 @@ properties: description: Register bits of stop mode control, the format is <&gpr req_gpr req_bit>. + fsl,pps-channel: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + description: + Specifies to which timer instance the PPS signal is routed. + enum: [0, 1, 2, 3] + mdio: $ref: mdio.yaml# unevaluatedProperties: false