| Message ID | 20241010-dts_qcs615-v1-1-05f27f6ac4d3@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | Enable ethernet on qcs615 | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Not a local patch |
On 10.10.2024 5:05 AM, Yijie Yang wrote: > Add ethqos ethernet controller node for QCS615 SoC. > > Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs615.dtsi | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > index 0d8fb557cf48..ba737cd89679 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > @@ -420,6 +420,33 @@ soc: soc@0 { > #address-cells = <2>; > #size-cells = <2>; > > + ethernet: ethernet@20000 { > + compatible = "qcom,qcs615-ethqos", "qcom,sm8150-ethqos"; > + reg = <0x0 0x20000 0x0 0x10000>, > + <0x0 0x36000 0x0 0x100>; Please pad the address part to 8 hex digits with leading zeroes > + reg-names = "stmmaceth", "rgmii"; > + > + clocks = <&gcc GCC_EMAC_AXI_CLK>, > + <&gcc GCC_EMAC_SLV_AHB_CLK>, > + <&gcc GCC_EMAC_PTP_CLK>, > + <&gcc GCC_EMAC_RGMII_CLK>; > + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; Please make this a vertical list, just like clocks Konrad
On 2024-11-16 03:11, Konrad Dybcio wrote: > On 10.10.2024 5:05 AM, Yijie Yang wrote: >> Add ethqos ethernet controller node for QCS615 SoC. >> >> Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcs615.dtsi | 27 +++++++++++++++++++++++++++ >> 1 file changed, 27 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> index 0d8fb557cf48..ba737cd89679 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> @@ -420,6 +420,33 @@ soc: soc@0 { >> #address-cells = <2>; >> #size-cells = <2>; >> >> + ethernet: ethernet@20000 { >> + compatible = "qcom,qcs615-ethqos", "qcom,sm8150-ethqos"; >> + reg = <0x0 0x20000 0x0 0x10000>, >> + <0x0 0x36000 0x0 0x100>; > > Please pad the address part to 8 hex digits with leading zeroes > >> + reg-names = "stmmaceth", "rgmii"; >> + >> + clocks = <&gcc GCC_EMAC_AXI_CLK>, >> + <&gcc GCC_EMAC_SLV_AHB_CLK>, >> + <&gcc GCC_EMAC_PTP_CLK>, >> + <&gcc GCC_EMAC_RGMII_CLK>; >> + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; > > Please make this a vertical list, just like clocks Sure, I will revise. > > Konrad
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index 0d8fb557cf48..ba737cd89679 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -420,6 +420,33 @@ soc: soc@0 { #address-cells = <2>; #size-cells = <2>; + ethernet: ethernet@20000 { + compatible = "qcom,qcs615-ethqos", "qcom,sm8150-ethqos"; + reg = <0x0 0x20000 0x0 0x10000>, + <0x0 0x36000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + + clocks = <&gcc GCC_EMAC_AXI_CLK>, + <&gcc GCC_EMAC_SLV_AHB_CLK>, + <&gcc GCC_EMAC_PTP_CLK>, + <&gcc GCC_EMAC_RGMII_CLK>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; + + interrupts = <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_lpi"; + + power-domains = <&gcc EMAC_GDSC>; + iommus = <&apps_smmu 0x1c0 0x0>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <20480>; + + status = "disabled"; + }; + gcc: clock-controller@100000 { compatible = "qcom,qcs615-gcc"; reg = <0 0x00100000 0 0x1f0000>;
Add ethqos ethernet controller node for QCS615 SoC. Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)