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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Tariq Toukan Subject: [PATCH net-next 10/15] net/mlx5: Simplify QoS scheduling element configuration Date: Sun, 13 Oct 2024 09:45:35 +0300 Message-ID: <20241013064540.170722-11-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241013064540.170722-1-tariqt@nvidia.com> References: <20241013064540.170722-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD81:EE_|SA1PR12MB7293:EE_ X-MS-Office365-Filtering-Correlation-Id: ee12194f-683f-41ee-daa4-08dceb52d40c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: hNeLnc3VRC3x1m8846ugROKYXSEehwlj3AF8zmJo+UlWLEzwgs3CldD6Z1LBaGrEj7wh61VsRvxoFziQEFkhgmKRIDTKrJv0A4ktm+oPFlJWgMoN+mUARol5aJw9bSWczZdyTeV6EKHW9BOKwg7Zpks9gR6WTdycn6XDgS2x/VovJnqa/pX2vBCoVYQDIJRYv7gQLdx0e2u3/ISSIyIAV1m8FQlNQnJqsOGBIHfOSd+M4Rm7y+uHzn6BZ51vufOy0xViRAjDnPYXEP1sI9zO610CZeVgmJh2MTMVgxxWZJ6Vhetsac5ae+UG1JFvY3w3hnHKNWUgvk/iZcMVhr8yTyJd/Ctc8Ly1Cvsj2Kfv01PoJ1L3oM4jo97Bz58judHfSSgyJWQKfFoL+uprZ24ZPMI0MSJTJkGBQ9+9Z9QT/l7eyxtXMVahrOgnAxwx43uO5mFboKor6teIovJgpo70rysIlF5sfjA43BfUFoyH+7jfoJ5Hs2zgUEMJJrdT7APA8c7+C55XYXoRosnCG/6IsFR/x8n7ruW3E2M8iO7bVhtfrKaZ+eCZM3ZLF7bMyICGvLH+PT2avPYeD2oa9cao1F7KhUYqOmj0FEw4Dv5st9LjlXeJB+qqiVZga6NoKRCaaS5fp5NJ86aTgR/39nrEtxjqCzTgLSOrBnhvQYlKBBicarCzP41jPCQQ8f8TKTCrh/YcuKrQvyCtmV1vAxPZC9cxR6JYjyfDsPOqfrGDkAvXFZC7kSLnPghWghtm7eYomqfqEuYYPQrdbKqb/eyqmnKffhPPTUyj76Aa0UVd6lCME2eCmBV1Gtm6sA0+ga7N73YExRp8OZ1DIjAOKUyZzc+gRTAcIElaxgoTiyMaaDs0zeIyXzq7HP46VWGxmnn4AHYyyjp62m7Vq3EPpH17saBO4H/kjSwMj1DBmgiG/RHqFicoJljNJJnU//V0j0IUk2BjIcn71h7MjyUmIRTiql75chkb3xNyu00p8jxNb9kHJsCAWhHzmmFz3emJEaBwsipbRf+BxeBzSSIab10+1y9iFGeTjw+c/Z7peRQZO6Hp+0TIeKS59VvYRJsjrByIxmZEf/5Ai+EM7cmmhKBRegQDIvZPRP+lG3/1ERbvC7C+4dGMBSl0A1QnejrayWU4Wt4drrkjRinJyTDlIVlOh+3YHMDxjRCHaanI3B5YKvCJxg+vtKRYcM7EmcKYSRILlUbWn3jzpVRkdxO29dzuW/yGnbrJ50UhvhltQoCjei1qAP7nCx5PA/fWd49LHu0ceL7Kbo/f3rMuNbQ0gVwqSMRZgIMgSl1alMcQIoVVSc6rrs3pJkaWF2+it6qSmGsJBYnYF5gqH0tEm2BZgHOEcmsi7r5XgP6Za8sDmHsyAcH15xw0fVy2Njw3wyxmvuQK X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2024 06:46:55.5819 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee12194f-683f-41ee-daa4-08dceb52d40c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD81.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7293 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Simplify the configuration of QoS scheduling elements by removing the separate functions `esw_qos_node_config` and `esw_qos_vport_config`. Instead, directly use the existing `esw_qos_sched_elem_config` function for both nodes and vports. This unification helps in generalizing operations on scheduling elements nodes. Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 86 +++++++++---------- 1 file changed, 40 insertions(+), 46 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index 0f465de4a916..ffd5d4d38fe5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -66,6 +66,11 @@ enum sched_node_type { SCHED_NODE_TYPE_VPORT, }; +static const char * const sched_node_type_str[] = { + [SCHED_NODE_TYPE_VPORTS_TSAR] = "vports TSAR", + [SCHED_NODE_TYPE_VPORT] = "vport", +}; + struct mlx5_esw_sched_node { u32 ix; /* Bandwidth parameters. */ @@ -113,11 +118,27 @@ mlx5_esw_qos_vport_get_parent(const struct mlx5_vport *vport) return vport->qos.sched_node->parent; } -static int esw_qos_sched_elem_config(struct mlx5_core_dev *dev, u32 sched_elem_ix, - u32 max_rate, u32 bw_share) +static void esw_qos_sched_elem_config_warn(struct mlx5_esw_sched_node *node, int err) +{ + if (node->vport) { + esw_warn(node->esw->dev, + "E-Switch modify %s scheduling element failed (vport=%d,err=%d)\n", + sched_node_type_str[node->type], node->vport->vport, err); + return; + } + + esw_warn(node->esw->dev, + "E-Switch modify %s scheduling element failed (err=%d)\n", + sched_node_type_str[node->type], err); +} + +static int esw_qos_sched_elem_config(struct mlx5_esw_sched_node *node, u32 max_rate, u32 bw_share, + struct netlink_ext_ack *extack) { u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {}; + struct mlx5_core_dev *dev = node->esw->dev; u32 bitmask = 0; + int err; if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling)) return -EOPNOTSUPP; @@ -127,46 +148,22 @@ static int esw_qos_sched_elem_config(struct mlx5_core_dev *dev, u32 sched_elem_i bitmask |= MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW; bitmask |= MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE; - return mlx5_modify_scheduling_element_cmd(dev, - SCHEDULING_HIERARCHY_E_SWITCH, - sched_ctx, - sched_elem_ix, - bitmask); -} - -static int esw_qos_node_config(struct mlx5_esw_sched_node *node, - u32 max_rate, u32 bw_share, struct netlink_ext_ack *extack) -{ - struct mlx5_core_dev *dev = node->esw->dev; - int err; - - err = esw_qos_sched_elem_config(dev, node->ix, max_rate, bw_share); - if (err) - NL_SET_ERR_MSG_MOD(extack, "E-Switch modify node TSAR element failed"); - - trace_mlx5_esw_node_qos_config(dev, node, node->ix, bw_share, max_rate); - - return err; -} - -static int esw_qos_vport_config(struct mlx5_vport *vport, - u32 max_rate, u32 bw_share, - struct netlink_ext_ack *extack) -{ - struct mlx5_esw_sched_node *vport_node = vport->qos.sched_node; - struct mlx5_core_dev *dev = vport_node->parent->esw->dev; - int err; - - err = esw_qos_sched_elem_config(dev, vport_node->ix, max_rate, bw_share); + err = mlx5_modify_scheduling_element_cmd(dev, + SCHEDULING_HIERARCHY_E_SWITCH, + sched_ctx, + node->ix, + bitmask); if (err) { - esw_warn(dev, - "E-Switch modify vport scheduling element failed (vport=%d,err=%d)\n", - vport->vport, err); - NL_SET_ERR_MSG_MOD(extack, "E-Switch modify vport scheduling element failed"); + esw_qos_sched_elem_config_warn(node, err); + NL_SET_ERR_MSG_MOD(extack, "E-Switch modify scheduling element failed"); + return err; } - trace_mlx5_esw_vport_qos_config(dev, vport, bw_share, max_rate); + if (node->type == SCHED_NODE_TYPE_VPORTS_TSAR) + trace_mlx5_esw_node_qos_config(dev, node, node->ix, bw_share, max_rate); + else if (node->type == SCHED_NODE_TYPE_VPORT) + trace_mlx5_esw_vport_qos_config(dev, node->vport, bw_share, max_rate); return 0; } @@ -246,8 +243,7 @@ static int esw_qos_normalize_node_min_rate(struct mlx5_esw_sched_node *node, if (bw_share == vport_node->bw_share) continue; - err = esw_qos_vport_config(vport_node->vport, vport_node->max_rate, bw_share, - extack); + err = esw_qos_sched_elem_config(vport_node, vport_node->max_rate, bw_share, extack); if (err) return err; @@ -274,7 +270,7 @@ static int esw_qos_normalize_min_rate(struct mlx5_eswitch *esw, struct netlink_e if (bw_share == node->bw_share) continue; - err = esw_qos_node_config(node, node->max_rate, bw_share, extack); + err = esw_qos_sched_elem_config(node, node->max_rate, bw_share, extack); if (err) return err; @@ -340,8 +336,7 @@ static int esw_qos_set_vport_max_rate(struct mlx5_vport *vport, if (!max_rate) act_max_rate = vport_node->parent->max_rate; - err = esw_qos_vport_config(vport, act_max_rate, vport_node->bw_share, extack); - + err = esw_qos_sched_elem_config(vport_node, act_max_rate, vport_node->bw_share, extack); if (!err) vport_node->max_rate = max_rate; @@ -386,7 +381,7 @@ static int esw_qos_set_node_max_rate(struct mlx5_esw_sched_node *node, if (node->max_rate == max_rate) return 0; - err = esw_qos_node_config(node, max_rate, node->bw_share, extack); + err = esw_qos_sched_elem_config(node, max_rate, node->bw_share, extack); if (err) return err; @@ -397,8 +392,7 @@ static int esw_qos_set_node_max_rate(struct mlx5_esw_sched_node *node, if (vport_node->max_rate) continue; - err = esw_qos_vport_config(vport_node->vport, max_rate, vport_node->bw_share, - extack); + err = esw_qos_sched_elem_config(vport_node, max_rate, vport_node->bw_share, extack); if (err) NL_SET_ERR_MSG_MOD(extack, "E-Switch vport implicit rate limit setting failed");