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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Tariq Toukan Subject: [PATCH net-next 04/15] net/mlx5: Restrict domain list insertion to root TSAR ancestors Date: Sun, 13 Oct 2024 09:45:29 +0300 Message-ID: <20241013064540.170722-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241013064540.170722-1-tariqt@nvidia.com> References: <20241013064540.170722-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7F:EE_|SA3PR12MB7923:EE_ X-MS-Office365-Filtering-Correlation-Id: 40df5ff8-2a81-4f14-0bf4-08dceb52cb36 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: ljQ6CceWTEKDzEbcshPg7H1gu3ZkyWe0gphFCgTfbVf45dvWG6t716jGttruse/pi5VD6xdIrj0ILpDdRVlKNAExgiqm8pYz301oZ+3J3Q3JMfIvYdbu6r+m9pDvvL/nTo+ZmpemmF4TVtj3/XT0ftvJ3YZ66HYAcO3g1byZYgZeYIMRoNEgNexZmZGfG1W7FtW/6FyIxC3cExAMV0HTNkzrTXm8VF1fh7IAdIxdPWrdud2es2lnFYLbl9hq8pDINHtAieLdAdAvmEq4sn4jptiU/TjdBqjFCu6UD9rVeCHTkYOwW53FSQbMAoMkZbbhHmWH10mhu4VjqhgnS5GZSYHR6CZgBvlmngSbPHntxihAxC6l1vcKXRu7aXOd+WdtJJsB1mUzgRrhgw6uNh2Pd+QQyj691rFURELtwIQX9tdwC6Drs3mvkiAt/qzkuHaeV0pYCHzV7irXXrFLzjAKggMYDpWKjsP3wxoT58VhwO/S7abURUlJPNW/F2mtny1zk6yAVsbE8Mc7TtOvFbJwteWzrPJqnZfUJvYjJHzj2yhXyAcDpkug7UVs7XVZo55ZEmmbv0PwzEpwO2BhanMfXH3kh3Iex7TyLZ1uT/eZBEpiEbVjF0jpiFlVA4LTpKr2IEJ2ovUITXTt9ATbkejn18sMQUoUVPD6GHcXd59iXn3yjS3lPwJsGxE5vsSL9ngu+1N4AW2ckVNaf8FIOZyZf9P5Tq8Ldk8ymVx66xHjfcGi+oBcdDm4MwMpd2ycfj68ny38XhcQymKe96PDt8nnIyp5korgKGP/miLasV5i/eOhe6RcK3uNcOHyScQWGyH0eAlnqjWgJYri4wvN7BtkbBIMHQP0nfYA7QCM3Dwcoq9XT31lESCKn3BmDXCooNrSZhJtSW5DebjNS+I4ns7lEBaB+vwoOgoNon78Sk0xMr52ooHwQI5zefY5O2/Jpx3sz9RvfSYJrXlyh+Vd6cGzwH0rWhYkWt6SA3M3gCh3U9dNJD3tVNCwuK/6uv0v3QORHWW/eb4GVEsfHvlxWL+xFgD3y/mz3omnafMHS2Eb/+tLUekEROQdXEhAAPSGoN3PkgT1iQuMH1lcKbhG8jWXaqaXkoZfVVK+Tny3e0hFcWTZ1FXMmleqJG4m5RywgYuHzzs5qkt4iGsDPvlOEHwwN8KhjFQN+OvTiWK2zM45PPUAurPUAc2V0VWYIS/jkEsAq6QsD0lp/21vmBCRl43I0X73LB/1Al3nsm3Sno26h2WTJR/mC1nAaD5T1SscZi2v7BZ1tWxZnA14kgNDY/4UMnJWUwDsBxR0w/AO1sB1+xfQYXwKTz0hh0KLY7a+lfTxs+zmGRWeNS3gCCuKBiE82QAzfXMccy4sRUW7MyX/MTg= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2024 06:46:40.7367 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40df5ff8-2a81-4f14-0bf4-08dceb52cb36 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7923 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Update the logic for adding rate groups to the E-Switch domain list, ensuring only groups with the root Transmit Scheduling Arbiter as their parent are included. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index e9ddd7f4ac80..65fd346d0e91 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -511,6 +511,7 @@ __esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_nod struct mlx5_esw_rate_group *parent) { struct mlx5_esw_rate_group *group; + struct list_head *parent_list; group = kzalloc(sizeof(*group), GFP_KERNEL); if (!group) @@ -521,7 +522,9 @@ __esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_nod group->type = type; group->parent = parent; INIT_LIST_HEAD(&group->members); - list_add_tail(&group->parent_entry, &esw->qos.domain->groups); + parent_list = parent ? &parent->members : &esw->qos.domain->groups; + list_add_tail(&group->parent_entry, parent_list); + return group; }