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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Tariq Toukan Subject: [PATCH net-next V3 01/15] net/mlx5: Refactor QoS group scheduling element creation Date: Wed, 16 Oct 2024 20:36:03 +0300 Message-ID: <20241016173617.217736-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004685:EE_|CH2PR12MB4199:EE_ X-MS-Office365-Filtering-Correlation-Id: 01af8ba3-4d9a-495c-ddba-08dcee09314b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: 0QrlJBHxv62I1IqXKNLewVYgBoQz3vDSYnlhCnPwnN00f1YQNA7mZIFs61qiSSAw4jwFtTdiJ2wbrLl4NNQKWz1RGAHv8z4/6LXEHOV1QCh/z6sDLIOzqrvlaopGV4jVdhJcZBEILttmJz2ZdWuhJ+u43nelPy5gvV0O1zc7YrBWP91/y0RE2aRKrep3bPnFrKH4BOpDTix3qgqBiQ3L7+RgQiz59MmmgHMtEfxRBmSizCJAP0aRVKHzbHoU+X6to1qiC7YG8iOJhwMMP9UfdaCgTiX+B6ey2ksPezWwJ6U+mk8VM30+DBx1C7mCKpBy3DEO8mTOK9jAySu4cn38e/1F8WT4uwkNRiTcnGOQ59JfmozMX100vf+9I230WN3RsJ9kycQf1ifUL3tgvpqmmEw4WCmAqwBihByW1SgbZ/VjKhmcSy6Iwes8xQEivY2Iky4YBQUDT6NkY5ErdY90JWytnnWNqYjOr/c2uf+LeAhT8d6wmcIhmXJa7nIpqUimVDnwdH21nClhe+ZM2NTF6rFPWDE4YpmgK0MnSAZ57qwlbssIQ12fUskoZsxY0zbPJ7A6Qct6KShJn6hSYyE0ppmXyF5m9+9IRriREjKSHNIMGhEtYp8BY15Bu2E4Uz5CNapfMNzIl8Y1vcDZjkWKGdA88SUZhiAsIYZ+KWBqQWzuwSZ+2/w3rKOt5PqhBH0hwTO5cL8FPR/Sy5340RTokotND17+5v/skYmoHe9yBwlloQm5kUqvKdDQtZsYRb0CN7kmasNeqQZSl73Z9P/zkHagsfhkNP68QED9w76el0ccGME6pvPiIC+6QTgmifj/SNUqo5fpGCo9vMrZZ8zKtPHqYSmE1UWHq0CTwQUSLSaZzQZecW9Bn7Lj8ip/SlPk2KMZUvMfH5+I4vxCuU7SJebDKdjeVhlWMN/bIVhkxAMKqZFA2kH6PzTFsYEtTdmZbK6t/ydHGijIW+T1u6TGTrSikYey31DtHpveC+PZPfGwYxA0at9DrQryMNlMYyaWi5Xip2GYKhe4LwCIiozxXJ5p1PV7xMCYhxOn83BJ9BzoYzkR5VU/aQZaq8EeGUSy64HGjWNbYWDh3Afa5XM+sXWpjNKJItg/hOcn8yDTMCDi74D3IBskkv05I3KH9EZ6Tn0xOqsxXj9VU4BvBIedAuAUJji/aXROImzaM4l74lNB4ffQlEsJJr5l/aDPCjGaQOYlCuy1qAe0i0toK/uo6cxsV4R+5OPcAZVLLN82hYRKM0+p3HsBNNhSeFMRhMvD1Cn0aqEHtgMu40h/2EwVD+IdKPpd/I+tDR1bagJN9AGXjx1sn2rd1XjDEJSXtRgX6+hNbgRX95SBEOpBvbNjKJ4OhAZRNylDNZVsO3lOQscnWYPU6NdoCN/1Ap5JJpkC X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:37:22.6908 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 01af8ba3-4d9a-495c-ddba-08dcee09314b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004685.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4199 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Introduce `esw_qos_create_group_sched_elem` to handle the creation of group scheduling elements for E-Switch QoS, Transmit Scheduling Arbiter (TSAR). This reduces duplication and simplifies code for TSAR setup. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Daniel Machon --- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 64 +++++++++---------- 1 file changed, 31 insertions(+), 33 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index ee6f76a6f0b5..7732f948e9c6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -371,6 +371,33 @@ static int esw_qos_set_group_max_rate(struct mlx5_esw_rate_group *group, return err; } +static int esw_qos_create_group_sched_elem(struct mlx5_core_dev *dev, u32 parent_element_id, + u32 *tsar_ix) +{ + u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {}; + void *attr; + + if (!mlx5_qos_element_type_supported(dev, + SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR, + SCHEDULING_HIERARCHY_E_SWITCH) || + !mlx5_qos_tsar_type_supported(dev, + TSAR_ELEMENT_TSAR_TYPE_DWRR, + SCHEDULING_HIERARCHY_E_SWITCH)) + return -EOPNOTSUPP; + + MLX5_SET(scheduling_context, tsar_ctx, element_type, + SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR); + MLX5_SET(scheduling_context, tsar_ctx, parent_element_id, + parent_element_id); + attr = MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes); + MLX5_SET(tsar_element, attr, tsar_type, TSAR_ELEMENT_TSAR_TYPE_DWRR); + + return mlx5_create_scheduling_element_cmd(dev, + SCHEDULING_HIERARCHY_E_SWITCH, + tsar_ctx, + tsar_ix); +} + static int esw_qos_vport_create_sched_element(struct mlx5_vport *vport, u32 max_rate, u32 bw_share) { @@ -496,21 +523,11 @@ static void __esw_qos_free_rate_group(struct mlx5_esw_rate_group *group) static struct mlx5_esw_rate_group * __esw_qos_create_rate_group(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack) { - u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {}; struct mlx5_esw_rate_group *group; - int tsar_ix, err; - void *attr; + u32 tsar_ix; + int err; - MLX5_SET(scheduling_context, tsar_ctx, element_type, - SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR); - MLX5_SET(scheduling_context, tsar_ctx, parent_element_id, - esw->qos.root_tsar_ix); - attr = MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes); - MLX5_SET(tsar_element, attr, tsar_type, TSAR_ELEMENT_TSAR_TYPE_DWRR); - err = mlx5_create_scheduling_element_cmd(esw->dev, - SCHEDULING_HIERARCHY_E_SWITCH, - tsar_ctx, - &tsar_ix); + err = esw_qos_create_group_sched_elem(esw->dev, esw->qos.root_tsar_ix, &tsar_ix); if (err) { NL_SET_ERR_MSG_MOD(extack, "E-Switch create TSAR for group failed"); return ERR_PTR(err); @@ -591,32 +608,13 @@ static int __esw_qos_destroy_rate_group(struct mlx5_esw_rate_group *group, static int esw_qos_create(struct mlx5_eswitch *esw, struct netlink_ext_ack *extack) { - u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {}; struct mlx5_core_dev *dev = esw->dev; - void *attr; int err; if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling)) return -EOPNOTSUPP; - if (!mlx5_qos_element_type_supported(dev, - SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR, - SCHEDULING_HIERARCHY_E_SWITCH) || - !mlx5_qos_tsar_type_supported(dev, - TSAR_ELEMENT_TSAR_TYPE_DWRR, - SCHEDULING_HIERARCHY_E_SWITCH)) - return -EOPNOTSUPP; - - MLX5_SET(scheduling_context, tsar_ctx, element_type, - SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR); - - attr = MLX5_ADDR_OF(scheduling_context, tsar_ctx, element_attributes); - MLX5_SET(tsar_element, attr, tsar_type, TSAR_ELEMENT_TSAR_TYPE_DWRR); - - err = mlx5_create_scheduling_element_cmd(dev, - SCHEDULING_HIERARCHY_E_SWITCH, - tsar_ctx, - &esw->qos.root_tsar_ix); + err = esw_qos_create_group_sched_elem(esw->dev, 0, &esw->qos.root_tsar_ix); if (err) { esw_warn(dev, "E-Switch create root TSAR failed (%d)\n", err); return err;