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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Simon Horman , Daniel Machon , Tariq Toukan Subject: [PATCH net-next V3 04/15] net/mlx5: Restrict domain list insertion to root TSAR ancestors Date: Wed, 16 Oct 2024 20:36:06 +0300 Message-ID: <20241016173617.217736-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241016173617.217736-1-tariqt@nvidia.com> References: <20241016173617.217736-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004683:EE_|LV3PR12MB9187:EE_ X-MS-Office365-Filtering-Correlation-Id: e770b8d4-5beb-44ee-0df2-08dcee09393a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: mOHxDtiTsyHBrNGtzfBW5dGg79P8naW+jfyV0ZVxQpWTkO2t6StvfK8XVmn1ZlCNijmg0Nc2N9PrJelXTuH49k6+4WG7scZXLdBvt3RdTr9xzzPG/Lp93OdgGHtRq5GxfKdG6GFT6SEWfcpBhJSuWQwZbqTr8V2fQ/5LmRjRHbKRD1wMBudsWq3XJc3qBED8k+JtR5VUAFs1WlSEoRnk9TPiYkAWeEDu6DTkVRAiqy9t2nNBYNMU3ol5AOrxePBjiDjRc5ArxHkTwTRqzAbrawGq4j9TatuK/HIXTuakdnm6aJlJ8dOZzlgaik2ZmKoj7o6TKbH0Yml/olphmvQyDTj04owGXB2tqkl7DYUOIJ7/QLRYDhBDGZPmO5t/qV9iKbvCQNWzNXANgmc736ioVqIroYuiV1/1n8diJ5J7mCbncTmrcEJBPeYfTCnDYeWnnkmV4Mx6MpTJ4ujR2QD0FCs3oDAoeG6p8D5rJUYGQGW5uaxBzFhBvHHH4IN5PjsYyehgQ8beqdf2uB/GyegOff0En6OYZ2THvzEGAuUKWFECMM9uSvDXOJMoVDY0VIld6WIqdMQ1vFbC+UYXWHcZP04wJxeEhhWkSz1wVDJLuLk+/+OHFuww0YWzk+rlAUNI9aiEpDHDGrIUw54pa+Tp1Czz0fVl+nV5S6lSvD3TtlZwZhFe3/PEfWPAPh/p5TKITqN2UDHaytV0zh+pyRITvpNI7DMMoQFKXzXA9YhWmWQRqvbkR7L8a7vPcCaXvcvyP+sRgbOM1OcBNxFvAxLQrA/Iv+Ffx62Glffko1VzCG5iNKMuQmv75nqnltiMc1FzAXEA/PPSXfgUtSuqQYZ7clZ453fcm7ojJCGqSHiZYyw3KriFIIST3VN3bKc6zzKF9RjCHs6d7QEfoMz6PC1L2wrehvNnXJ6lwEOu/SgwDElWMBxzDuBSE4p/s99q4vb4Ahi0ZsYk+NukfXqmDmZuKG1fqjRG/8j/qny8yOaid6g+2e5nSSFclTsE0b00/QturH3Z3RFaFp2OvaOR+LP90dPIYROScfgh2Z8YZrM6LwWfHZ/LvWhA/LL5yLKomzF1ORwgwm7eFPcfcxUOtAe33lIH7eQnMrdlbM3/167UGnOLlZehzWgAU7e9XNfadD85bRKR1WQBH27W1rGu6zsTYXY9vZH9BRIKSqAF4DcOPA6RmfHL5GSEvAY5LMY0l9ChbVIIWXiLB2mozGd68zC2J1P8VfahYIDtGdb0DpMGFOBskEohi/0ITOKxeDy+bErhfacH5BboOGAPJOYV1afPVGpYffSDvzQDVhYrQPnXARMvY1vJhV35Iqs4aaY1N+KgqTk+NCjirrTVHoNOb1jJHF1CzCJ6ru3Egb4mJy4SU4I= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2024 17:37:35.9958 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e770b8d4-5beb-44ee-0df2-08dcee09393a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004683.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9187 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Update the logic for adding rate groups to the E-Switch domain list, ensuring only groups with the root Transmit Scheduling Arbiter as their parent are included. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan Reviewed-by: Daniel Machon --- drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index f2a0d59fa5bb..dd6fe729f456 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -511,6 +511,7 @@ __esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_nod struct mlx5_esw_rate_group *parent) { struct mlx5_esw_rate_group *group; + struct list_head *parent_list; group = kzalloc(sizeof(*group), GFP_KERNEL); if (!group) @@ -521,7 +522,9 @@ __esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_nod group->type = type; group->parent = parent; INIT_LIST_HEAD(&group->members); - list_add_tail(&group->parent_entry, &esw->qos.domain->groups); + parent_list = parent ? &parent->members : &esw->qos.domain->groups; + list_add_tail(&group->parent_entry, parent_list); + return group; }