Message ID | 20241017032213.22256-4-SkyLake.Huang@mediatek.com (mailing list archive) |
---|---|
State | Accepted |
Commit | 93a610c00ffd8b9c7c108039d894ddd5193b147e |
Delegated to: | Netdev Maintainers |
Headers | show |
Series | net: phy: Refactor mediatek-ge-soc.c for clarity and correctness | expand |
On Thu, Oct 17, 2024 at 11:22:13AM +0800, Sky Huang wrote: > From: "SkyLake.Huang" <skylake.huang@mediatek.com> > > This patch propagates error code correctly in cal_cycle() > and improve with FIELD_GET(). > > Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> Reviewed-by: Simon Horman <horms@kernel.org>
diff --git a/drivers/net/phy/mediatek-ge-soc.c b/drivers/net/phy/mediatek-ge-soc.c index 1d7719b..a931832 100644 --- a/drivers/net/phy/mediatek-ge-soc.c +++ b/drivers/net/phy/mediatek-ge-soc.c @@ -110,7 +110,7 @@ #define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) #define MTK_PHY_RG_AD_CAL_COMP 0x17a -#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) +#define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8) #define MTK_PHY_RG_AD_CAL_CLK 0x17b #define MTK_PHY_DA_CAL_CLK BIT(0) @@ -351,8 +351,10 @@ static int cal_cycle(struct phy_device *phydev, int devad, phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, MTK_PHY_DA_CALIN_FLAG); - ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> - MTK_PHY_AD_CAL_COMP_OUT_SHIFT; + ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP); + if (ret < 0) + return ret; + ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret); phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); return ret;