| Message ID | 20241017165225.21206-7-alejandro.lucero-palau@amd.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | cxl: add Type2 device support | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Guessing tree name failed - patch did not apply |
On 10/17/24 11:52 AM, alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero <alucerop@amd.com> > > Create a new function for a type2 device initialising > cxl_dev_state struct regarding cxl regs setup and mapping. > > Signed-off-by: Alejandro Lucero <alucerop@amd.com> > --- > drivers/cxl/core/pci.c | 47 +++++++++++++++++++++++++++++++++++++++++ > include/linux/cxl/cxl.h | 2 ++ > 2 files changed, 49 insertions(+) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index 99acc258722d..f0f7e8bd4499 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -1141,6 +1141,53 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > } > EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL); > > +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, > + struct cxl_dev_state *cxlds) > +{ > + struct cxl_register_map map; > + int rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, > + cxlds->capabilities); > + /* > + * This call returning a non-zero value is not considered an error since > + * these regs are not mandatory for Type2. If they do exist then mapping > + * them should not fail. > + */ > + if (rc) > + return 0; > + > + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); > +} I think you can use this function for type 3 device set up in cxl_pci_probe() as well with a minor change. Instead of if (rc) return 0; above, you could do if (rc) { if (cxlds->type == CXL_DEVTYPE_CLASSMEM) return rc; return 0; } instead and replace the memdev cxl_pci_setup_regs() call in cxl_pci_probe(). > +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) > +{ > + int rc; > + > + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); > + if (rc) > + return rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > + &cxlds->reg_map, cxlds->capabilities); > + if (rc) { > + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); > + return rc; > + } > + > + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) > + return rc; If you make the modification above, I think this is just a drop-in replacement for the component register set up code in cxl_pci_probe(). I may be wrong (it's EOD here and my brain is a little tired), but it could be a nice cleanup if so. > + > + rc = cxl_map_component_regs(&cxlds->reg_map, > + &cxlds->regs.component, > + BIT(CXL_CM_CAP_CAP_ID_RAS)); > + if (rc) > + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); > + > + return rc; > +} > +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, CXL); > + > bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, > unsigned long *current_caps) > { > diff --git a/include/linux/cxl/cxl.h b/include/linux/cxl/cxl.h > index 78653fa4daa0..2f48ee591259 100644 > --- a/include/linux/cxl/cxl.h > +++ b/include/linux/cxl/cxl.h > @@ -5,6 +5,7 @@ > #define __CXL_H > > #include <linux/device.h> > +#include <linux/pci.h> > > enum cxl_resource { > CXL_RES_DPA, > @@ -52,4 +53,5 @@ int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res, > bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, > unsigned long *expected_caps, > unsigned long *current_caps); > +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds); > #endif
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 99acc258722d..f0f7e8bd4499 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1141,6 +1141,53 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, } EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL); +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, + struct cxl_dev_state *cxlds) +{ + struct cxl_register_map map; + int rc; + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, + cxlds->capabilities); + /* + * This call returning a non-zero value is not considered an error since + * these regs are not mandatory for Type2. If they do exist then mapping + * them should not fail. + */ + if (rc) + return 0; + + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); +} + +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) +{ + int rc; + + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); + if (rc) + return rc; + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, + &cxlds->reg_map, cxlds->capabilities); + if (rc) { + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); + return rc; + } + + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) + return rc; + + rc = cxl_map_component_regs(&cxlds->reg_map, + &cxlds->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS)); + if (rc) + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); + + return rc; +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, CXL); + bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, unsigned long *current_caps) { diff --git a/include/linux/cxl/cxl.h b/include/linux/cxl/cxl.h index 78653fa4daa0..2f48ee591259 100644 --- a/include/linux/cxl/cxl.h +++ b/include/linux/cxl/cxl.h @@ -5,6 +5,7 @@ #define __CXL_H #include <linux/device.h> +#include <linux/pci.h> enum cxl_resource { CXL_RES_DPA, @@ -52,4 +53,5 @@ int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res, bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, unsigned long *current_caps); +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds); #endif