From patchwork Thu Oct 24 22:34:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13849821 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2087.outbound.protection.outlook.com [40.107.20.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24AF7219492; Thu, 24 Oct 2024 22:35:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.20.87 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729809318; cv=fail; b=j9YA2vZqgldhxaGXEUNeZtc+GHkP5ZICX/VXmvPKgyU6TJfWLhwq+LjCrHtTNURLIHdaLVjh9+8UXy5HQRXHLvs+TbnBPkaE8mGXaaRudUbEtjRIe21J5OGA2IJ9KevpDc5NtLG8S58/UMpLFenb1QPxebsEBg7hwKPX/yHk/AY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729809318; c=relaxed/simple; bh=++Ra5UUPQByKYlOdODjlqMpR2reTqaPcz/EXBHMKqmo=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=TGItrHVedDyuMhw6dO+ZentrkcA2oHyEwNEmtLVvuNJsdftCExQtt9V968OENF9seKXxy5n/QZ6A/6j6Tvym1+crdMa1ZVCaHBdnBMEu+A965oXaqCNr9klCGu6l+p7nbU6L3+oV6gOLuDWAjmdUD5dubeY30lrHKjMpQf/erug= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b=NhKjr2Vb; arc=fail smtp.client-ip=40.107.20.87 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b="NhKjr2Vb" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=VD6hsDcwD+8N1eNnQGc0xuT5JeiIkOCK5unUsTWaLYTBJPn9Lix2nrcbE1+Bt8v/aSENZl94JrUGFpQPJ57UB465MAp4mtkajPauxbZQ5xpGdq/9bc+wU3F3iSrm/8nYtgrUlnGj2PtOlkum9he64azqvvoIkKtFZFfxZP8Ev3mpZNPDIlM2KOTroFIbAy4wHXI73ZzgQMUVC8lgFfKkFdtu8SWHkxai2JBGp/0ZLTBROtfKau43wjqFP4SK0YOIhCho4SwR18FjbUbF0PC5bDXL3kAmL0McORKSXFF5/PcljOU5vilmQxZfU+ieZP0Evx+CcUJAyTBaSu9/L06H3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Sw1r65JSYmrG2SKNClARjtA2eh894aOhfoVKCDGVrxg=; b=UkG8FfIDiB6afFbdjoHcJgn/fUH/pC7ei/WCsFcGAH+hx0Oh0E4iZMwyn7Kz+aePwEEPnkJtja4tffg2zXdG+jUrWD3UWbHCJ884weP/Jc31YhS0JwweZEUm7tlT+2RlETNtjS51F66fWlYFJ03qIRVfKIBgWjs2WCzRGUPmdGkCD7hXTyr9V2siSLpUX/3IgTFeGvCn5/gzTKmdgZKn3+F7WDvrGQfOEDF4wf4uOOa5ueu7UWmsnMIM4EyANgnjXV9XLeFX6VRbq3UTLI+xtoN4P95nSTgLxagvbONOuNert4/zpAEIDW8PWJFUHiDBhd4gYXUTeZaReH5q2x9h1g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Sw1r65JSYmrG2SKNClARjtA2eh894aOhfoVKCDGVrxg=; b=NhKjr2Vb1Py968TsDzn3cjpJADr/URphKDe01L9NEgjuEHNPq9h1nawV3CUYz56ien/ScFYVVJMALpvnN56WzbyhRadcHgHGOOV1NqxJCIWQrCkUtHLPig0pab7WPrSECSZmAcD4mQR5rXB9VrKnW1TGTOmnvPrNtW08s4N3Od/kAH0Jd1Kszb+vAnX+yWSKqSkjrsnsaLnsntREFyfAkjmbcfUJPs3g4YuTt7wwy7hsSNloFMFWnh6AZEEkx30PAqAjVkPlYbiHLxIwVjI+HrHWIOKCm2tQp5+Y1ybwwApUdn7GRkMnvn6pm2ESzMeMBhcx7t2nAcrGeAh8wa3N4A== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by AM7PR04MB7189.eurprd04.prod.outlook.com (2603:10a6:20b:116::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.20; Thu, 24 Oct 2024 22:35:12 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%4]) with mapi id 15.20.8069.024; Thu, 24 Oct 2024 22:35:12 +0000 From: Frank Li Date: Thu, 24 Oct 2024 18:34:45 -0400 Subject: [PATCH v3 2/2] PCI: imx6: Add IOMMU and ITS MSI support for i.MX95 Message-Id: <20241024-imx95_lut-v3-2-7509c9bbab86@nxp.com> References: <20241024-imx95_lut-v3-0-7509c9bbab86@nxp.com> In-Reply-To: <20241024-imx95_lut-v3-0-7509c9bbab86@nxp.com> To: Bjorn Helgaas , Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, Frank.li@nxp.com, alyssa@rosenzweig.io, bpf@vger.kernel.org, broonie@kernel.org, jgg@ziepe.ca, joro@8bytes.org, l.stach@pengutronix.de, lgirdwood@gmail.com, maz@kernel.org, p.zabel@pengutronix.de, robin.murphy@arm.com, will@kernel.org, Robin Murphy , Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1729809293; l=7490; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=++Ra5UUPQByKYlOdODjlqMpR2reTqaPcz/EXBHMKqmo=; b=Xnj1jOlE/HzeXRsQUoFRSJNlKXL//4xmQphSrwpQd7/t83Iv82dDXfA3EJ+n3bgH9AZkSGDGs ix+4FTCLsaTBF5t6H41A/uqaNdROkSdnZAW++8S9SExrUt5gy6ba13P X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: BYAPR05CA0001.namprd05.prod.outlook.com (2603:10b6:a03:c0::14) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|AM7PR04MB7189:EE_ X-MS-Office365-Filtering-Correlation-Id: 43cb1f34-51cd-48a5-ea34-08dcf47c1f94 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|52116014|7416014|376014|921020|38350700014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?N5pw1TkXGabZnP1wFz2upqKyBxb09zW?= =?utf-8?q?6GNZA5W+gKdoCG9Vl9Y7YG5XgJ/oWrCe/Aq91UiMCLvtE8ZkBOyrARl2/+MEzhBXt?= =?utf-8?q?syQtlWMeBGJC0EwaFuE72gN6p2mKpPtjuylxjBUO1yBbAbPvlrR1/TWBlF/sOmMBQ?= =?utf-8?q?E1QqQdAxt7gUQ+kl82szvoYoOYbYNz3vqkBGCyhYK/n9LeFWOHh0noRyM4bjmWuPi?= =?utf-8?q?a8KP+HO3D8JHhIhmWg0l0pWmnOrnZkkSS4gdHl7BY7PAP0MwjFIRx9Rg1zlj4jBTe?= =?utf-8?q?dLZw6jdkfn9xnEHSp38LakLd6iy3qTSEqwUB9CnkHlO4k0G8tJUm58WjnZgdrZpDv?= =?utf-8?q?RWdpa87QjI9vuU63/MH7km1QP3jcqrMS4fzuJ2bjuOmRkpIzPtuExC8ZPHF22EhXV?= =?utf-8?q?V2CaqdKIRxs5SBKuAhliWZSG7qjjHsef16PP0CVcBIyznV3cpWVnrXRITUmwvYSFA?= =?utf-8?q?IK3UFldkyefyQ4Wnka5SEZ7K0tl1wHKYzUe3rC5BYceVUwSMEICjSPyITqjmOhN7H?= =?utf-8?q?6sJJgLvNcseoaTQ3X0GL2wk2Lwkde9Yqe50Vq8L8r1gmC2z03BtQ9jGiI3sCYe10+?= =?utf-8?q?s2VwWQC+rSaZfIzpOdkxMbq2LDgWge9nko099NCUk0fEKdBrq+Vi8gQVCAM447ucx?= =?utf-8?q?zAmzyFwuou2NF9M1so7Eb67zgdBYMrvdxkO6pN5OkhBBAz/D+QfdeIfSgdx0TpuH7?= =?utf-8?q?gPOQZ6gpAekDbMwXuAXsdWUWNGXFOSxb4oR+hAOAUhMA/lCfMVL7MjQfJGYXDlNvT?= =?utf-8?q?JvF8ljQzD6V0RHnBiRAHsD/juF3umEbGmURgMqJ7ZZi8wTD+yzSScbjFJVO5UT5MK?= =?utf-8?q?AyvzV8nVSFtmhHtwFL/tJmGZHBMGTfEF1cb+xlzctMejXInpECqxieUiCXLQ4ZfnQ?= =?utf-8?q?LWdQKH4KcE+2tFLEOsMdmeEI1cDvJhbOUDPS07cb4SThoUeEU+T1TCZ/E9Z99R8fr?= =?utf-8?q?Kx7kpdmUUuQeMhIBgfAuTpHesBnIbaPYA7R/fYq3OCOTXIZ/VuZrA0b4IAGG9GmUE?= =?utf-8?q?2B9IijYpEhi93rJwMh5Xl0xGzsIfVbpPKX6A4tgSZY+pkBSKhkLLHzP5vXc9ny3tf?= =?utf-8?q?78uLIilwWWbwGQ8hZ2oRG3Bd4vTvrENxQ5PJJkXjXemBPQ4RnoQdJ3PBlpuN8upwT?= =?utf-8?q?Vq3aGwyIDdYtBYc6lDtCFF5KN7O/+WTdy03xAkL/RvPoXfl/bVnNDYDs6VOkaFvrz?= =?utf-8?q?KuNDPhyIIf1mvSWtvsQrZAemXgdUaVBCG+mhCGPyoEZyKikZxEByAs2wYU21YrgCq?= =?utf-8?q?DueehnLQPkoacQhqse4lK/FaKmx4zR3W9XuXKEhsIv1cXPWqtMg91aWnklRp+9e5m?= =?utf-8?q?Abw/Z0pRmTVM?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(52116014)(7416014)(376014)(921020)(38350700014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?8b5qIDxzXSKZlekD9P7AwkS7de26?= =?utf-8?q?VUWvs3GWNMRlYcmmy9XB9BHpghROXFSq/PAzBifqfmqaJvD0eUr7iwOJ7TZXHFZL2?= =?utf-8?q?1x4pwhrIHfUXDp7skmFB7RG1t8KV/Ag1fUKctaYHpNUAiSuJM9Ajni7Nw6Qb+/s12?= =?utf-8?q?A0S8h16/KvvH82qyAm2Yul39WD0Ot0wn0zySftNgVMeUJkBMC/U/doWxHaqPNaa8w?= =?utf-8?q?Z+ahAXwJ4JTNnnsNJ+EBnOyulyC3/MfrDfZ/8FKke6YGKvsnxhz0oLR9Bljcu/FJX?= =?utf-8?q?phBFdkwQHRHmPuC4kyrlDS1eURqnyI4ul0uelcHdp7JcpodOJsEziP8KzgD1yg8Zg?= =?utf-8?q?bMGk42u64i8vML8TXbQzhAZa6MeVXSl/yfc/3t2Zo0HtnTAoFrPEmYbm+LgsNDFDt?= =?utf-8?q?ZEOmiNSwkXkrREkd0ESBsjxLITJa0k+37pNjczK9pt0/jm1K0oMXmPx+6nToNJSlI?= =?utf-8?q?77CkPutz/FQ/NxF7TZ196Se5FenlQ+zxoETVKJ6B8txzWLcnxJmjqd5wPcvzAIlZv?= =?utf-8?q?On53lRKORndwkEytoPuTQZKSFlpb2ro5UPNvHE1Bwa04cxvE4nQPOHTiVO3Q439W2?= =?utf-8?q?QcoSLrbfy4orX3dw4zFUZ0f9uJ/2aREiqYBdbxidH+NY+88gouhrBm2kq4WotswOl?= =?utf-8?q?YKNvLv8EqTcRfPbPpv4X232Lq2l6M5E+CWg6Zfh9NuqY7W4vF9YzFNpLptk5X1d6Y?= =?utf-8?q?+so9ztTwMrByrtyA7XXbNNUPw3PqJhUOQUcmrXKLwIihgrOFO5792ULuwk1e7PJ2B?= =?utf-8?q?jqCwNEVrFVpWJCzS+dx9yVVvsxFWB6SKjfDx/B+8QvSSyqHhD3mLcwSTcuzooNmWL?= =?utf-8?q?r+0R3R5MdLaF2Jp8KC+ISVxwiagpcT0w8E35QwRgoYdxxn1de/GnqxsdLm4+lQoes?= =?utf-8?q?qkia+LyL1gF7mErndjgxRzJAozBLH16DmEP6jndgVR/RATaBOIIkGdgyJn6yQXvQr?= =?utf-8?q?cWJxmYzZGJ/rA6wuYoMXI2vijMJ7EC4OuRYx1k7UgSxDSanjejAtBWPDCd9Lhbv/d?= =?utf-8?q?3EFPFTjSVQWb6lZB+vwJYKJDg2PkljMHzaWUbwSI7tUEjaPmYdo2mUFTuvGOSfU7Z?= =?utf-8?q?r9+l8AqLEFILDW/Rde+FODvkrUcY4cYa7Gkhx4G03vN3O5OK+/ZkGJPlfiqnxmhKw?= =?utf-8?q?ilDwJ6jEf02mSY6vGdA66X9edNgwxdQudbpybBA6wjNu6XGI8mwxaub4NN2jBFMoV?= =?utf-8?q?ao8A/kk6aUu08CXrbzFPxU1S+QQ+XHsHs+vaf97AvKe0OtUuFmVSUiwHwqDE9gSH2?= =?utf-8?q?EDuZiOgeP8pPAM7jhrBujKXymGH2uUIWobcfA99Zjw0UvZ3pgcYnvDZkrZnpSdIx8?= =?utf-8?q?715AG2ccwFjQMvCOHVuczi7oybH6UkF/fsExnH2zgi5tUo0ZsOb0abPQDNYW3SQRS?= =?utf-8?q?4bmDsm4BB2T7huS/hZ2AEURcNCzrW2+TdKsbDOsjvfm0+lXn89a5Ir1Xj/VPs9w3c?= =?utf-8?q?lG6Q8IXUiibT+Krrg3lnwsGj1/ri9CY+K7mID1CZ929iZKLlrdcxkNBFvrGfbcyWm?= =?utf-8?q?01dPhs1dr29R?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 43cb1f34-51cd-48a5-ea34-08dcf47c1f94 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Oct 2024 22:35:12.3398 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: vFj2j/i2g/JxjIZRqe8E2tZ+HSJWyXTL7U6vFY+8ud2XV/iWyyqQmxvoqwhfEgG2NHnADkLtmDJXl8Svgeinvw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR04MB7189 For the i.MX95, configuration of a LUT is necessary to convert Bus Device Function (BDF) to stream IDs, which are utilized by both IOMMU and ITS. This involves examining the msi-map and smmu-map to ensure consistent mapping of PCI BDF to the same stream IDs. Subsequently, LUT-related registers are configured. In the absence of an msi-map, the built-in MSI controller is utilized as a fallback. Additionally, register a PCI bus callback function enable_device() and disable_device() to config LUT when enable a new PCI device. Signed-off-by: Frank Li --- Change from v2 to v3 - Use the "target" argument of of_map_id() - Check if rid already in lut table when enable device change from v1 to v2 - set callback to pci_host_bridge instead pci->ops. --- drivers/pci/controller/dwc/pci-imx6.c | 159 +++++++++++++++++++++++++++++++++- 1 file changed, 158 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 94f3411352bf0..95f06bfb9fc5e 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -55,6 +55,22 @@ #define IMX95_PE0_GEN_CTRL_3 0x1058 #define IMX95_PCIE_LTSSM_EN BIT(0) +#define IMX95_PE0_LUT_ACSCTRL 0x1008 +#define IMX95_PEO_LUT_RWA BIT(16) +#define IMX95_PE0_LUT_ENLOC GENMASK(4, 0) + +#define IMX95_PE0_LUT_DATA1 0x100c +#define IMX95_PE0_LUT_VLD BIT(31) +#define IMX95_PE0_LUT_DAC_ID GENMASK(10, 8) +#define IMX95_PE0_LUT_STREAM_ID GENMASK(5, 0) + +#define IMX95_PE0_LUT_DATA2 0x1010 +#define IMX95_PE0_LUT_REQID GENMASK(31, 16) +#define IMX95_PE0_LUT_MASK GENMASK(15, 0) + +#define IMX95_SID_MASK GENMASK(5, 0) +#define IMX95_MAX_LUT 32 + #define to_imx_pcie(x) dev_get_drvdata((x)->dev) enum imx_pcie_variants { @@ -82,6 +98,7 @@ enum imx_pcie_variants { #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) +#define IMX_PCIE_FLAG_HAS_LUT BIT(8) #define imx_check_flag(pci, val) (pci->drvdata->flags & val) @@ -134,6 +151,7 @@ struct imx_pcie { struct device *pd_pcie_phy; struct phy *phy; const struct imx_pcie_drvdata *drvdata; + struct mutex lock; }; /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ @@ -925,6 +943,137 @@ static void imx_pcie_stop_link(struct dw_pcie *pci) imx_pcie_ltssm_disable(dev); } +static int imx_pcie_add_lut(struct imx_pcie *imx_pcie, u16 reqid, u8 sid) +{ + struct dw_pcie *pci = imx_pcie->pci; + struct device *dev = pci->dev; + u32 data1, data2; + int i; + + if (sid >= 64) { + dev_err(dev, "Invalid SID for index %d\n", sid); + return -EINVAL; + } + + guard(mutex)(&imx_pcie->lock); + + for (i = 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_RWA | i); + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); + + if (!(data1 & IMX95_PE0_LUT_VLD)) + continue; + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); + + /* Needn't add duplicated Request ID */ + if (reqid == FIELD_GET(IMX95_PE0_LUT_REQID, data2)) + return 0; + } + + for (i = 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_RWA | i); + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); + if (data1 & IMX95_PE0_LUT_VLD) + continue; + + data1 = FIELD_PREP(IMX95_PE0_LUT_DAC_ID, 0); + data1 |= FIELD_PREP(IMX95_PE0_LUT_STREAM_ID, sid); + data1 |= IMX95_PE0_LUT_VLD; + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, data1); + + data2 = 0xffff; + data2 |= FIELD_PREP(IMX95_PE0_LUT_REQID, reqid); + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, data2); + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, i); + + return 0; + } + + dev_err(dev, "All lut already used\n"); + return -EINVAL; +} + +static void imx_pcie_remove_lut(struct imx_pcie *imx_pcie, u16 reqid) +{ + u32 data2 = 0; + int i; + + guard(mutex)(&imx_pcie->lock); + + for (i = 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_RWA | i); + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); + if (FIELD_GET(IMX95_PE0_LUT_REQID, data2) == reqid) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, 0); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, 0); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, i); + + break; + } + } +} + +static int imx_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_dev *pdev) +{ + u32 sid_i = 0, sid_m = 0, rid = pci_dev_id(pdev); + struct device_node *target; + struct imx_pcie *imx_pcie; + struct device *dev; + int err_i, err_m; + + imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); + dev = imx_pcie->pci->dev; + + target = NULL; + err_i = of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask", &target, &sid_i); + target = NULL; + err_m = of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask", &target, &sid_m); + + + /* + * msi-map iommu-map + * Y Y ITS + SMMU, require the same sid + * Y N ITS + * N Y DWC MSI Ctrl + SMMU + * N N DWC MSI Ctrl + */ + if (!err_i && !err_m) + if ((sid_i & IMX95_SID_MASK) != (sid_m & IMX95_SID_MASK)) { + dev_err(dev, "its and iommu stream id miss match, please check dts file\n"); + return -EINVAL; + } + + /* + * Both iommu-map and msi-map not exist, use dwc built-in MSI + * controller, do nothing here. + */ + if (err_i && err_m) + return 0; + + if (!err_i) + return imx_pcie_add_lut(imx_pcie, rid, sid_i); + + if (!err_m) + /* Hardware auto add 2 bit controller id ahead of stream ID */ + return imx_pcie_add_lut(imx_pcie, rid, sid_m & IMX95_SID_MASK); + + return 0; +} + +static void imx_pcie_disable_device(struct pci_host_bridge *bridge, struct pci_dev *pdev) +{ + struct imx_pcie *imx_pcie; + + imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); + imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev)); +} + static int imx_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -941,6 +1090,11 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) } } + if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) { + pp->bridge->enable_device = imx_pcie_enable_device; + pp->bridge->disable_device = imx_pcie_disable_device; + } + imx_pcie_assert_core_reset(imx_pcie); if (imx_pcie->drvdata->init_phy) @@ -1292,6 +1446,8 @@ static int imx_pcie_probe(struct platform_device *pdev) imx_pcie->pci = pci; imx_pcie->drvdata = of_device_get_match_data(dev); + mutex_init(&imx_pcie->lock); + /* Find the PHY if one is defined, only imx7d uses it */ np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); if (np) { @@ -1587,7 +1743,8 @@ static const struct imx_pcie_drvdata drvdata[] = { }, [IMX95] = { .variant = IMX95, - .flags = IMX_PCIE_FLAG_HAS_SERDES, + .flags = IMX_PCIE_FLAG_HAS_SERDES | + IMX_PCIE_FLAG_HAS_LUT, .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), .ltssm_off = IMX95_PE0_GEN_CTRL_3,