| Message ID | 20241028-upstream_s32cc_gmac-v4-16-03618f10e3e2@oss.nxp.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | Add support for Synopsis DWMAC IP on NXP Automotive SoCs S32G2xx/S32G3xx/S32R45 | expand |
On Mon, Oct 28, 2024 at 09:24:58PM +0100, Jan Petrous via B4 Relay wrote: > From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com> > > The PTP clock is read by stmmac_platform during DT parse. > On S32G/R the clock is not ready and returns 0. Postpone > reading of the clock on PTP init. This needs more explanation as to why this is a feature, not a bug, for the PTP clock. Andrew
On Tue, Oct 29, 2024 at 01:18:43PM +0100, Andrew Lunn wrote: > On Mon, Oct 28, 2024 at 09:24:58PM +0100, Jan Petrous via B4 Relay wrote: > > From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com> > > > > The PTP clock is read by stmmac_platform during DT parse. > > On S32G/R the clock is not ready and returns 0. Postpone > > reading of the clock on PTP init. > > This needs more explanation as to why this is a feature, not a bug, > for the PTP clock. > Thanks for comment. I did a homework and found out the root cause is using PTP clocks before they are properly enabled. As I understand, the clocks, especially the composite variant, require preparation and/or enabling them, what is not managed correctly for PTP clocks when stmmac_platform is used. In this case, the PTP clock value is read this way: stmmac_probe_config_dt: // https://github.com/torvalds/linux/blob/4a5df37964673effcd9f84041f7423206a5ae5f2/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c#L634 /* Fall-back to main clock in case of no PTP ref is passed */ plat->clk_ptp_ref = devm_clk_get(&pdev->dev, "ptp_ref"); if (IS_ERR(plat->clk_ptp_ref)) { plat->clk_ptp_rate = clk_get_rate(plat->stmmac_clk); plat->clk_ptp_ref = NULL; dev_info(&pdev->dev, "PTP uses main clock\n"); } else { plat->clk_ptp_rate = clk_get_rate(plat->clk_ptp_ref); dev_dbg(&pdev->dev, "PTP rate %d\n", plat->clk_ptp_rate); } If I change getter to enabled getter: plat->clk_ptp_ref = devm_clk_get_enabled(&pdev->dev, "ptp_ref"); The driver got valid rate and the patch is not needed anymore. So, if I didn't miss something, it seems like I have to replace the current patch with one fixing clk getter. BR. /Jan
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c index fba221c37594..da2cdcfd0529 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c @@ -140,6 +140,18 @@ static void s32_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode) dev_err(gmac->dev, "Can't set tx clock\n"); } +static void s32_dwmac_ptp_clk_freq_config(struct stmmac_priv *priv) +{ + struct plat_stmmacenet_data *plat = priv->plat; + + if (!plat->clk_ptp_ref) + return; + + plat->clk_ptp_rate = clk_get_rate(plat->clk_ptp_ref); + + netdev_dbg(priv->dev, "PTP rate %lu\n", plat->clk_ptp_rate); +} + static int s32_dwmac_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat; @@ -195,6 +207,7 @@ static int s32_dwmac_probe(struct platform_device *pdev) plat->init = s32_gmac_init; plat->exit = s32_gmac_exit; plat->fix_mac_speed = s32_fix_mac_speed; + plat->ptp_clk_freq_config = s32_dwmac_ptp_clk_freq_config; plat->bsp_priv = gmac;