[2/4] arm64: dts: agilex5: add gmac nodes

Message ID	20241030-v6-12-topic-socfpga-agilex5-v1-2-b2b67780e60e@pengutronix.de (mailing list archive)
State	Not Applicable
Headers	show Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C19761E906A for <netdev@vger.kernel.org>; Wed, 30 Oct 2024 12:10:25 +0000 (UTC) From: Steffen Trumtrar <s.trumtrar@pengutronix.de> Date: Wed, 30 Oct 2024 13:10:13 +0100 Subject: [PATCH 2/4] arm64: dts: agilex5: add gmac nodes Precedence: bulk MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20241030-v6-12-topic-socfpga-agilex5-v1-2-b2b67780e60e@pengutronix.de> References: <20241030-v6-12-topic-socfpga-agilex5-v1-0-b2b67780e60e@pengutronix.de> In-Reply-To: <20241030-v6-12-topic-socfpga-agilex5-v1-0-b2b67780e60e@pengutronix.de> To: Dinh Nguyen <dinguyen@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Richard Cochran <richardcochran@gmail.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org> Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-clk@vger.kernel.org, kernel@pengutronix.de, Steffen Trumtrar <s.trumtrar@pengutronix.de>
Series	ARM64: dts: intel: agilex5: add nodes and new board \| expand [0/4] ARM64: dts: intel: agilex5: add nodes and new board [1/4] arm64: dts: agilex5: add gpio0 [2/4] arm64: dts: agilex5: add gmac nodes [3/4] dt-bindings: intel: add agilex5-based Arrow AXE5-Eagle [4/4] arm64: dts: agilex5: initial support for Arrow AXE5-Eagle

Context	Check	Description
netdev/tree_selection	success	Not a local patch

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 57c28e284cccdb99ede6cea2bc0e8dd8aaf47fe9..761d970f8de59e08275edf15a9c890ba3bb1404c 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -141,6 +141,327 @@ soc: soc@0 { device_type = "soc"; interrupt-parent = <&intc>; + gmac0: ethernet@10810000 { + compatible = "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg = <0x10810000 0x3500>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + max-frame-size = <3800>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <32768>; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + clocks = <&clkmgr AGILEX5_EMAC0_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + snps,axi-config = <&stmmac_axi_emac0_setup>; + snps,mtl-rx-config = <&mtl_rx_emac0_setup>; + snps,mtl-tx-config = <&mtl_tx_emac0_setup>; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + status = "disabled"; + + stmmac_axi_emac0_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac0_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + mtl_tx_emac0_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x9>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight = <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight = <0x0B>; + snps,dcb-algorithm; + }; + queue3 { + snps,weight = <0x0C>; + snps,dcb-algorithm; + }; + queue4 { + snps,weight = <0x0D>; + snps,dcb-algorithm; + }; + queue5 { + snps,weight = <0x0E>; + snps,dcb-algorithm; + }; + queue6 { + snps,weight = <0x0F>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + queue7 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + }; + }; + + gmac1: ethernet@10820000 { + compatible = "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg = <0x10820000 0x3500>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + max-frame-size = <3800>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <32768>; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + clocks = <&clkmgr AGILEX5_EMAC1_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + snps,axi-config = <&stmmac_axi_emac1_setup>; + snps,mtl-rx-config = <&mtl_rx_emac1_setup>; + snps,mtl-tx-config = <&mtl_tx_emac1_setup>; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + status = "disabled"; + + stmmac_axi_emac1_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac1_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + mtl_tx_emac1_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x9>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight = <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight = <0x0B>; + snps,dcb-algorithm; + }; + queue3 { + snps,weight = <0x0C>; + snps,dcb-algorithm; + }; + queue4 { + snps,weight = <0x0D>; + snps,dcb-algorithm; + }; + queue5 { + snps,weight = <0x0E>; + snps,dcb-algorithm; + }; + queue6 { + snps,weight = <0x0F>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + queue7 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + }; + }; + + gmac2: ethernet@10830000 { + compatible = "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg = <0x10830000 0x3500>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + max-frame-size = <3800>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <32768>; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + clocks = <&clkmgr AGILEX5_EMAC2_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + snps,axi-config = <&stmmac_axi_emac2_setup>; + snps,mtl-rx-config = <&mtl_rx_emac2_setup>; + snps,mtl-tx-config = <&mtl_tx_emac2_setup>; + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + status = "disabled"; + + stmmac_axi_emac2_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + + mtl_rx_emac2_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x2>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x3>; + }; + queue4 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x4>; + }; + queue5 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x5>; + }; + queue6 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x6>; + }; + queue7 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x7>; + }; + }; + + mtl_tx_emac2_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x9>; + snps,dcb-algorithm; + }; + queue1 { + snps,weight = <0x0A>; + snps,dcb-algorithm; + }; + queue2 { + snps,weight = <0x0B>; + snps,dcb-algorithm; + }; + queue3 { + snps,weight = <0x0C>; + snps,dcb-algorithm; + }; + queue4 { + snps,weight = <0x0D>; + snps,dcb-algorithm; + }; + queue5 { + snps,weight = <0x0E>; + snps,dcb-algorithm; + }; + queue6 { + snps,weight = <0x0F>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + queue7 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,tbs-enable; + }; + }; + }; + clkmgr: clock-controller@10d10000 { compatible = "intel,agilex5-clkmgr"; reg = <0x10d10000 0x1000>;

[2/4] arm64: dts: agilex5: add gmac nodes

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