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Mon, 2 Dec 2024 11:12:42 -0600 Received: from xcbalucerop41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39 via Frontend Transport; Mon, 2 Dec 2024 11:12:41 -0600 From: To: , , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v6 07/28] sfc: use cxl api for regs setup and checking Date: Mon, 2 Dec 2024 17:12:01 +0000 Message-ID: <20241202171222.62595-8-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241202171222.62595-1-alejandro.lucero-palau@amd.com> References: <20241202171222.62595-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A9:EE_|CH3PR12MB8073:EE_ X-MS-Office365-Filtering-Correlation-Id: d44ca879-0649-416c-c9d0-08dd12f48b57 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2024 17:12:47.4803 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d44ca879-0649-416c-c9d0-08dd12f48b57 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8073 X-Patchwork-Delegate: kuba@kernel.org From: Alejandro Lucero Use cxl code for registers discovery and mapping. Validate capabilities found based on those registers against expected capabilities. Signed-off-by: Alejandro Lucero --- drivers/net/ethernet/sfc/efx_cxl.c | 19 +++++++++++++++++++ include/cxl/cxl.h | 2 ++ 2 files changed, 21 insertions(+) diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c index 9cfb519e569f..44e1061feba1 100644 --- a/drivers/net/ethernet/sfc/efx_cxl.c +++ b/drivers/net/ethernet/sfc/efx_cxl.c @@ -21,6 +21,8 @@ int efx_cxl_init(struct efx_probe_data *probe_data) { struct efx_nic *efx = &probe_data->efx; + DECLARE_BITMAP(expected, CXL_MAX_CAPS); + DECLARE_BITMAP(found, CXL_MAX_CAPS); struct pci_dev *pci_dev; struct efx_cxl *cxl; struct resource res; @@ -65,6 +67,23 @@ int efx_cxl_init(struct efx_probe_data *probe_data) goto err2; } + rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds); + if (rc) { + pci_err(pci_dev, "CXL accel setup regs failed"); + goto err2; + } + + bitmap_clear(expected, 0, CXL_MAX_CAPS); + bitmap_set(expected, CXL_DEV_CAP_HDM, 1); + bitmap_set(expected, CXL_DEV_CAP_RAS, 1); + + if (!cxl_pci_check_caps(cxl->cxlds, expected, found)) { + pci_err(pci_dev, + "CXL device capabilities found(%08lx) not as expected(%08lx)", + *found, *expected); + goto err2; + } + probe_data->cxl = cxl; return 0; diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index 05f06bfd2c29..18fb01adcf19 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -5,6 +5,7 @@ #define __CXL_H #include +#include enum cxl_resource { CXL_RES_DPA, @@ -40,4 +41,5 @@ int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res, bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, unsigned long *current_caps); +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds); #endif