From patchwork Tue Dec 3 23:53:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacob Keller X-Patchwork-Id: 13893102 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F013C20B1F3 for ; Tue, 3 Dec 2024 23:55:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733270115; cv=none; b=T860Sx/jMtXkufZOS2sNvU2scuLna9MF5PbKKHFp1tenCkEQJmWWJrGW204IWltHu7LxhYNCLOK8DTC9Qsy8V6VVwyxJC8BRrUv4lbn7w+nEqGUpNMk69eyRLCH3mOVQI7LNPLEEgodKdGJnNWpyG1eT8GS5NITDuuPtnLmAnHI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733270115; c=relaxed/simple; bh=vlPTS3FAWdK3o+4cWtfjRMFpmv8SowMTS/b1CJnPmYE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KWxzMrybzt57sIQlpoLOMGEMsBOEF0peHUhO1eWl1GvD6eiGE1TAR/eEd51kCYoiTqxoY7pN5d05Nq9MwIuizkZIORciA7E+B0MLaWHrrFQhuKck3TFVlsQ5bw7EG18aMW/Yfeus1ZOiH0xxSYs0mrcrpR2Il97OIzYRBaSiHD0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XN8247sj; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XN8247sj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1733270114; x=1764806114; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=vlPTS3FAWdK3o+4cWtfjRMFpmv8SowMTS/b1CJnPmYE=; b=XN8247sj/SiZ6Gs0MJXOmX9SVnRQHcfQ+PLazgBTLIWI+545JpMiI0sY WWUMJblmEbjEWg9/p2FklblRDwLCwQvBApW1LYRyZCbHb2s/eLOQY2DFM AdocPnb7GNAi+W13tQlkWb4pNHlJmeT+29tWiHnj6AeQwLK/0ES4jF5O0 BbVejRqeD+76Eio4mmQ6/Q5osjKjmXLbTO2FJ5tTDt1h9EIMUnlD9qWzF 3ftOs0HmbW+JNqHw32O9nU57t9PzUZGsWln3iUTsYshB8c33vWkUZWkrr ZqkqO9Okw+uE0SaKt4cA9Mez93QXp6iCCuZn6nXNJ0N6csQe9QgcjiuOZ w==; X-CSE-ConnectionGUID: 8IiC3oK4Qlq0pH3KjTBB2Q== X-CSE-MsgGUID: QG6ENHNsS/GhQPJRxwEDVw== X-IronPort-AV: E=McAfee;i="6700,10204,11275"; a="58918454" X-IronPort-AV: E=Sophos;i="6.12,206,1728975600"; d="scan'208";a="58918454" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2024 15:55:09 -0800 X-CSE-ConnectionGUID: Bpuj35E0QoWvNpvkmgK1VQ== X-CSE-MsgGUID: /z+AOWq1RguxCkOnPiFROQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,206,1728975600"; d="scan'208";a="93679057" Received: from jekeller-desk.jf.intel.com ([10.166.241.20]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Dec 2024 15:55:09 -0800 From: Jacob Keller Date: Tue, 03 Dec 2024 15:53:55 -0800 Subject: [PATCH net-next v8 09/10] ice: move prefetch enable to ice_setup_rx_ctx Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241203-packing-pack-fields-and-ice-implementation-v8-9-2ed68edfe583@intel.com> References: <20241203-packing-pack-fields-and-ice-implementation-v8-0-2ed68edfe583@intel.com> In-Reply-To: <20241203-packing-pack-fields-and-ice-implementation-v8-0-2ed68edfe583@intel.com> To: Vladimir Oltean , Andrew Morton , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Tony Nguyen , Przemek Kitszel , Masahiro Yamada , netdev Cc: Jacob Keller X-Mailer: b4 0.14.2 X-Patchwork-Delegate: kuba@kernel.org The ice_write_rxq_ctx() function is responsible for programming the Rx Queue context into hardware. It receives the configuration in unpacked form via the ice_rlan_ctx structure. This function unconditionally modifies the context to set the prefetch enable bit. This was done by commit c31a5c25bb19 ("ice: Always set prefena when configuring an Rx queue"). Setting this bit makes sense, since prefetching descriptors is almost always the preferred behavior. However, the ice_write_rxq_ctx() function is not the place that actually defines the queue context. We initialize the Rx Queue context in ice_setup_rx_ctx(). It is surprising to have the Rx queue context changed by a function who's responsibility is to program the given context to hardware. Following the principle of least surprise, move the setting of the prefetch enable bit out of ice_write_rxq_ctx() and into the ice_setup_rx_ctx(). Signed-off-by: Jacob Keller Reviewed-by: Przemek Kitszel --- drivers/net/ethernet/intel/ice/ice_base.c | 3 +++ drivers/net/ethernet/intel/ice/ice_common.c | 9 +++------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_base.c b/drivers/net/ethernet/intel/ice/ice_base.c index 5fe7b5a100202e6f0c33c617c604d45f9487b1f4..b2af8e3586f7620d372f2055e337485d102d3cbc 100644 --- a/drivers/net/ethernet/intel/ice/ice_base.c +++ b/drivers/net/ethernet/intel/ice/ice_base.c @@ -454,6 +454,9 @@ static int ice_setup_rx_ctx(struct ice_rx_ring *ring) /* Rx queue threshold in units of 64 */ rlan_ctx.lrxqthresh = 1; + /* Enable descriptor prefetch */ + rlan_ctx.prefena = 1; + /* PF acts as uplink for switchdev; set flex descriptor with src_vsi * metadata and flags to allow redirecting to PR netdev */ diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c index 1b013c9c937826633db8cbe29d8e1dc310c7b6f0..379040593d975342eaa2a3032938683b419f4f60 100644 --- a/drivers/net/ethernet/intel/ice/ice_common.c +++ b/drivers/net/ethernet/intel/ice/ice_common.c @@ -1430,14 +1430,13 @@ static void ice_pack_rxq_ctx(const struct ice_rlan_ctx *ctx, } /** - * ice_write_rxq_ctx + * ice_write_rxq_ctx - Write Rx Queue context to hardware * @hw: pointer to the hardware structure * @rlan_ctx: pointer to the rxq context * @rxq_index: the index of the Rx queue * - * Converts rxq context from sparse to dense structure and then writes - * it to HW register space and enables the hardware to prefetch descriptors - * instead of only fetching them on demand + * Pack the sparse Rx Queue context into dense hardware format and write it + * into the HW register space. */ int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, u32 rxq_index) @@ -1447,8 +1446,6 @@ int ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, if (!rlan_ctx) return -EINVAL; - rlan_ctx->prefena = 1; - ice_pack_rxq_ctx(rlan_ctx, &buf); return ice_copy_rxq_ctx_to_hw(hw, &buf, rxq_index);