diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
deleted file mode 100644
index 612a8e8abc88774619f4fd4e9205a3dd32226a9b..0000000000000000000000000000000000000000
--- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-Altera SOCFPGA SoC DWMAC controller
-
-This is a variant of the dwmac/stmmac driver an inherits all descriptions
-present in Documentation/devicetree/bindings/net/stmmac.txt.
-
-The device node has additional properties:
-
-Required properties:
- - compatible	: For Cyclone5/Arria5 SoCs it should contain
-		  "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
-		  "altr,socfpga-stmmac-a10-s10".
-		  Along with "snps,dwmac" and any applicable more detailed
-		  designware version numbers documented in stmmac.txt
- - altr,sysmgr-syscon : Should be the phandle to the system manager node that
-   encompasses the glue register, the register offset, and the register shift.
-   On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
-   on the Arria10/Stratix10/Agilex platforms, the register shift represents
-   bit for each emac to enable/disable signals from the FPGA fabric to the
-   EMAC modules.
- - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
-   for ptp ref clk. This affects all emacs as the clock is common.
-
-Optional properties:
-altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
-		DWMAC controller is connected emac splitter.
-phy-mode: The phy mode the ethernet operates in
-altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
-
-This device node has additional phandle dependency, the sgmii converter:
-
-Required properties:
- - compatible	: Should be altr,gmii-to-sgmii-2.0
- - reg-names	: Should be "eth_tse_control_port"
-
-Example:
-
-gmii_to_sgmii_converter: phy@100000240 {
-	compatible = "altr,gmii-to-sgmii-2.0";
-	reg = <0x00000001 0x00000240 0x00000008>,
-		<0x00000001 0x00000200 0x00000040>;
-	reg-names = "eth_tse_control_port";
-	clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>;
-	clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
-};
-
-gmac0: ethernet@ff700000 {
-	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
-	altr,sysmgr-syscon = <&sysmgr 0x60 0>;
-	reg = <0xff700000 0x2000>;
-	interrupts = <0 115 4>;
-	interrupt-names = "macirq";
-	mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
-	clocks = <&emac_0_clk>;
-	clock-names = "stmmaceth";
-	phy-mode = "sgmii";
-	altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
-};
diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.yaml b/Documentation/devicetree/bindings/net/socfpga-dwmac.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..022d9eb7011d47666b140aaecf54541ca3dec0ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/socfpga-dwmac.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/socfpga-dwmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera SOCFPGA SoC DWMAC controller
+
+maintainers:
+  - Dinh Nguyen <dinguyen@altera.com>
+
+description:
+  This is a variant of the dwmac/stmmac driver an inherits all descriptions
+  present in Documentation/devicetree/bindings/net/stmmac.txt.
+
+# We need a select here so we don't match all nodes with 'snps,dwmac'
+select:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - altr,socfpga-stmmac # For Cyclone5/Arria5 SoCs
+          - altr,socfpga-stmmac-a10-s10 # For Arria10/Agilex/Stratix10 SoCs
+  required:
+    - compatible
+
+allOf:
+  - $ref: snps,dwmac.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - altr,socfpga-stmmac
+          - const: snps,dwmac-3.70a
+      - items:
+          - enum:
+              - altr,socfpga-stmmac-a10-s10
+          - const: snps,dwmac-3.72a
+          - const: snps,dwmac
+      - items:
+          - enum:
+              - altr,socfpga-stmmac-a10-s10
+          - const: snps,dwmac-3.74a
+          - const: snps,dwmac
+
+  altr,sysmgr-syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to the sysmgr node
+          - description: register offset that controls the PHY mode or FPGA signals
+          - description: register shift for the PHY mode bits or FPGA signals
+    description:
+      Should be the phandle to the system manager node that
+      encompasses the glue register, the register offset, and the register shift.
+      On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
+      on the Arria10/Stratix10/Agilex platforms, the register shift represents
+      bit for each emac to enable/disable signals from the FPGA fabric to the
+      EMAC modules.
+
+  altr,f2h_ptp_ref_clk:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Use f2h_ptp_ref_clk instead of default eosc1 clock
+      for ptp ref clk. This affects all emacs as the clock is common.
+
+  altr,emac-splitter:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Should be the phandle to the emac splitter soft IP node if
+      DWMAC controller is connected emac splitter.
+
+  phy-mode:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      The phy mode the ethernet operates in.
+
+  altr,sgmii-to-sgmii-converter:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the TSE SGMII converter.
+
+      This device node has additional phandle dependency, the sgmii converter
+        - compatible that should be altr,gmii-to-sgmii-2.0
+        - reg-names that should be "eth_tse_control_port"
+
+required:
+  - compatible
+  - reg
+  - altr,sysmgr-syscon
+
+examples:
+  - |
+    //Example 1
+    gmii_to_sgmii_converter: phy@100000240 {
+          compatible = "altr,gmii-to-sgmii-2.0";
+          reg = <0x00000001 0x00000240 0x00000008>,
+                <0x00000001 0x00000200 0x00000040>;
+          reg-names = "eth_tse_control_port";
+          clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>;
+          clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk";
+    };
+
+  - |
+    //Example 2
+    gmac0: ethernet@ff700000 {
+          compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+          altr,sysmgr-syscon = <&sysmgr 0x60 0>;
+          reg = <0xff700000 0x2000>;
+          interrupts = <0 115 4>;
+          interrupt-names = "macirq";
+          mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+          clocks = <&emac_0_clk>;
+          clock-names = "stmmaceth";
+          phy-mode = "sgmii";
+          altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
+    };
