| Message ID | 20250205151950.25268-16-alucerop@amd.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | cxl: add type2 device basic support | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Guessing tree name failed - patch did not apply |
alucerop@ wrote: > From: Alejandro Lucero <alucerop@amd.com> [snip] > diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c > index 774e1cb4b1cb..a9ff84143e5d 100644 > --- a/drivers/net/ethernet/sfc/efx_cxl.c > +++ b/drivers/net/ethernet/sfc/efx_cxl.c > @@ -25,6 +25,7 @@ int efx_cxl_init(struct efx_probe_data *probe_data) > struct pci_dev *pci_dev = efx->pci_dev; > DECLARE_BITMAP(expected, CXL_MAX_CAPS); > DECLARE_BITMAP(found, CXL_MAX_CAPS); > + resource_size_t max_size; > struct mds_info sfc_mds_info; > struct efx_cxl *cxl; > > @@ -102,6 +103,24 @@ int efx_cxl_init(struct efx_probe_data *probe_data) > goto err_regs; > } > > + cxl->cxlrd = cxl_get_hpa_freespace(cxl->cxlmd, 1, > + CXL_DECODER_F_RAM | CXL_DECODER_F_TYPE2, Won't the addition of CXL_DECODER_F_TYPE2 cause this to fail? I'm not seeing CXL_DECODER_F_TYPE2 set on a decoder in any of the patches. So won't that make the flags check fail? Why is CXL_DECODER_F_RAM not enough? Ira [snip]
On 2/5/25 22:47, Ira Weiny wrote: > alucerop@ wrote: >> From: Alejandro Lucero <alucerop@amd.com> > [snip] > >> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c >> index 774e1cb4b1cb..a9ff84143e5d 100644 >> --- a/drivers/net/ethernet/sfc/efx_cxl.c >> +++ b/drivers/net/ethernet/sfc/efx_cxl.c >> @@ -25,6 +25,7 @@ int efx_cxl_init(struct efx_probe_data *probe_data) >> struct pci_dev *pci_dev = efx->pci_dev; >> DECLARE_BITMAP(expected, CXL_MAX_CAPS); >> DECLARE_BITMAP(found, CXL_MAX_CAPS); >> + resource_size_t max_size; >> struct mds_info sfc_mds_info; >> struct efx_cxl *cxl; >> >> @@ -102,6 +103,24 @@ int efx_cxl_init(struct efx_probe_data *probe_data) >> goto err_regs; >> } >> >> + cxl->cxlrd = cxl_get_hpa_freespace(cxl->cxlmd, 1, >> + CXL_DECODER_F_RAM | CXL_DECODER_F_TYPE2, > Won't the addition of CXL_DECODER_F_TYPE2 cause this to fail? I'm not > seeing CXL_DECODER_F_TYPE2 set on a decoder in any of the patches. So > won't that make the flags check fail? Why is CXL_DECODER_F_RAM not > enough? It does not fail. I have tested this and I know other people have had no issue with it. It seems the root decoders needs to have specific support for type2, so this is required. > Ira > > [snip]
Alejandro Lucero Palau wrote: > > On 2/5/25 22:47, Ira Weiny wrote: > > alucerop@ wrote: > >> From: Alejandro Lucero <alucerop@amd.com> > > [snip] > > > >> diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c > >> index 774e1cb4b1cb..a9ff84143e5d 100644 > >> --- a/drivers/net/ethernet/sfc/efx_cxl.c > >> +++ b/drivers/net/ethernet/sfc/efx_cxl.c > >> @@ -25,6 +25,7 @@ int efx_cxl_init(struct efx_probe_data *probe_data) > >> struct pci_dev *pci_dev = efx->pci_dev; > >> DECLARE_BITMAP(expected, CXL_MAX_CAPS); > >> DECLARE_BITMAP(found, CXL_MAX_CAPS); > >> + resource_size_t max_size; > >> struct mds_info sfc_mds_info; > >> struct efx_cxl *cxl; > >> > >> @@ -102,6 +103,24 @@ int efx_cxl_init(struct efx_probe_data *probe_data) > >> goto err_regs; > >> } > >> > >> + cxl->cxlrd = cxl_get_hpa_freespace(cxl->cxlmd, 1, > >> + CXL_DECODER_F_RAM | CXL_DECODER_F_TYPE2, > > Won't the addition of CXL_DECODER_F_TYPE2 cause this to fail? I'm not > > seeing CXL_DECODER_F_TYPE2 set on a decoder in any of the patches. So > > won't that make the flags check fail? Why is CXL_DECODER_F_RAM not > > enough? > > > It does not fail. I have tested this and I know other people have had no > issue with it. > > It seems the root decoders needs to have specific support for type2, so > this is required. Ah I see what happened. I got confused thinking this was a new bit because you defined it in the new .../include/cxl/cxl.h. But aren't these bits are already defined in ../drivers/cxl/cxl.h as the decoder bits? If so, we will need to promote those bit definitions to the common include file rather than redefine them. Ira
diff --git a/drivers/net/ethernet/sfc/Kconfig b/drivers/net/ethernet/sfc/Kconfig index 0ce4a9cd5590..f2bc7f5fbccf 100644 --- a/drivers/net/ethernet/sfc/Kconfig +++ b/drivers/net/ethernet/sfc/Kconfig @@ -69,6 +69,7 @@ config SFC_CXL bool "Solarflare SFC9100-family CXL support" depends on SFC && CXL_BUS && !(SFC=y && CXL_BUS=m) depends on CXL_BUS >= CXL_BUS + depends on CXL_REGION default SFC source "drivers/net/ethernet/sfc/falcon/Kconfig" diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c index 774e1cb4b1cb..a9ff84143e5d 100644 --- a/drivers/net/ethernet/sfc/efx_cxl.c +++ b/drivers/net/ethernet/sfc/efx_cxl.c @@ -25,6 +25,7 @@ int efx_cxl_init(struct efx_probe_data *probe_data) struct pci_dev *pci_dev = efx->pci_dev; DECLARE_BITMAP(expected, CXL_MAX_CAPS); DECLARE_BITMAP(found, CXL_MAX_CAPS); + resource_size_t max_size; struct mds_info sfc_mds_info; struct efx_cxl *cxl; @@ -102,6 +103,24 @@ int efx_cxl_init(struct efx_probe_data *probe_data) goto err_regs; } + cxl->cxlrd = cxl_get_hpa_freespace(cxl->cxlmd, 1, + CXL_DECODER_F_RAM | CXL_DECODER_F_TYPE2, + &max_size); + + if (IS_ERR(cxl->cxlrd)) { + pci_err(pci_dev, "cxl_get_hpa_freespace failed\n"); + rc = PTR_ERR(cxl->cxlrd); + goto err_regs; + } + + if (max_size < EFX_CTPIO_BUFFER_SIZE) { + pci_err(pci_dev, "%s: not enough free HPA space %pap < %u\n", + __func__, &max_size, EFX_CTPIO_BUFFER_SIZE); + rc = -ENOSPC; + cxl_put_root_decoder(cxl->cxlrd); + goto err_regs; + } + probe_data->cxl = cxl; return 0; @@ -114,8 +133,10 @@ int efx_cxl_init(struct efx_probe_data *probe_data) void efx_cxl_exit(struct efx_probe_data *probe_data) { - if (probe_data->cxl) + if (probe_data->cxl) { + cxl_put_root_decoder(probe_data->cxl->cxlrd); kfree(probe_data->cxl); + } } MODULE_IMPORT_NS("CXL");