diff mbox series

[v10,06/26] sfc: use cxl api for regs setup and checking

Message ID 20250205151950.25268-7-alucerop@amd.com (mailing list archive)
State Not Applicable
Delegated to: Netdev Maintainers
Headers show
Series cxl: add type2 device basic support | expand

Checks

Context Check Description
netdev/tree_selection success Guessing tree name failed - patch did not apply

Commit Message

Alejandro Lucero Palau Feb. 5, 2025, 3:19 p.m. UTC 
From: Alejandro Lucero <alucerop@amd.com>

Use cxl code for registers discovery and mapping.

Validate capabilities found based on those registers against expected
capabilities.

Signed-off-by: Alejandro Lucero <alucerop@amd.com>
Reviewed-by: Martin Habets <habetsm.xilinx@gmail.com>
Reviewed-by: Zhi Wang <zhi@nvidia.com>
Acked-by: Edward Cree <ecree.xilinx@gmail.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/net/ethernet/sfc/efx_cxl.c | 32 ++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

Comments

Ira Weiny Feb. 5, 2025, 9:31 p.m. UTC | #1 
alucerop@ wrote:
> From: Alejandro Lucero <alucerop@amd.com>
> 

I'm still going through the series to better understand the over all arch
you need.  But I did find a couple of minor issues so I'll make those
comments straight off.

[snip]

> @@ -46,9 +50,37 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
>  		return PTR_ERR(cxl->cxlmds);
>  	}
>  
> +	bitmap_clear(expected, 0, CXL_MAX_CAPS);
> +	set_bit(CXL_DEV_CAP_HDM, expected);
> +	set_bit(CXL_DEV_CAP_HDM, expected);

Why set HDM x2?

> +	set_bit(CXL_DEV_CAP_RAS, expected);
> +
> +	rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlmds, found);
> +	if (rc) {
> +		pci_err(pci_dev, "CXL accel setup regs failed");
> +		goto err_regs;
> +	}
> +
> +	/*
> +	 * Checking mandatory caps are there as, at least, a subset of those
> +	 * found.
> +	 */
> +	if (!bitmap_subset(expected, found, CXL_MAX_CAPS)) {
> +		pci_err(pci_dev,
> +			"CXL device capabilities found(%pb) not as expected(%pb)",
> +			found, expected);
> +		rc = -EIO;
> +		goto err_regs;
> +	}
> +
>  	probe_data->cxl = cxl;
>  
>  	return 0;
> +
> +err_regs:
> +	kfree(probe_data->cxl);

Is this freeing what you want here?  AFAICS probe_data->cxl is not set
until after the checks work.

I think this is best handled by using __free() on cxl and no_free_ptr()
when setting probe_data?

Ira

> +	return rc;
> +
>  }
>  
>  void efx_cxl_exit(struct efx_probe_data *probe_data)
> -- 
> 2.17.1
> 
>
Alejandro Lucero Palau Feb. 6, 2025, 5:47 p.m. UTC | #2 
On 2/5/25 21:31, Ira Weiny wrote:
> alucerop@ wrote:
>> From: Alejandro Lucero <alucerop@amd.com>
>>
> I'm still going through the series to better understand the over all arch
> you need.  But I did find a couple of minor issues so I'll make those
> comments straight off.
>
> [snip]
>
>> @@ -46,9 +50,37 @@ int efx_cxl_init(struct efx_probe_data *probe_data)
>>   		return PTR_ERR(cxl->cxlmds);
>>   	}
>>   
>> +	bitmap_clear(expected, 0, CXL_MAX_CAPS);
>> +	set_bit(CXL_DEV_CAP_HDM, expected);
>> +	set_bit(CXL_DEV_CAP_HDM, expected);
> Why set HDM x2?


Something went wrong applying the patch.

I'll fix it.


>
>> +	set_bit(CXL_DEV_CAP_RAS, expected);
>> +
>> +	rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlmds, found);
>> +	if (rc) {
>> +		pci_err(pci_dev, "CXL accel setup regs failed");
>> +		goto err_regs;
>> +	}
>> +
>> +	/*
>> +	 * Checking mandatory caps are there as, at least, a subset of those
>> +	 * found.
>> +	 */
>> +	if (!bitmap_subset(expected, found, CXL_MAX_CAPS)) {
>> +		pci_err(pci_dev,
>> +			"CXL device capabilities found(%pb) not as expected(%pb)",
>> +			found, expected);
>> +		rc = -EIO;
>> +		goto err_regs;
>> +	}
>> +
>>   	probe_data->cxl = cxl;
>>   
>>   	return 0;
>> +
>> +err_regs:
>> +	kfree(probe_data->cxl);
> Is this freeing what you want here?  AFAICS probe_data->cxl is not set
> until after the checks work.
>
> I think this is best handled by using __free() on cxl and no_free_ptr()
> when setting probe_data?
>
> Ira
>
>

Yes, that is right. I was eager to submit v10 and made silly mistakes.

I'll fix it.

Thanks!
diff mbox series

Patch

diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
index 69feffd4aec3..06d5ac531f34 100644
--- a/drivers/net/ethernet/sfc/efx_cxl.c
+++ b/drivers/net/ethernet/sfc/efx_cxl.c
@@ -22,8 +22,12 @@  int efx_cxl_init(struct efx_probe_data *probe_data)
 {
 	struct efx_nic *efx = &probe_data->efx;
 	struct pci_dev *pci_dev = efx->pci_dev;
+	DECLARE_BITMAP(expected, CXL_MAX_CAPS);
+	DECLARE_BITMAP(found, CXL_MAX_CAPS);
 	struct efx_cxl *cxl;
+
 	u16 dvsec;
+	int rc;
 
 	probe_data->cxl_pio_initialised = false;
 
@@ -46,9 +50,37 @@  int efx_cxl_init(struct efx_probe_data *probe_data)
 		return PTR_ERR(cxl->cxlmds);
 	}
 
+	bitmap_clear(expected, 0, CXL_MAX_CAPS);
+	set_bit(CXL_DEV_CAP_HDM, expected);
+	set_bit(CXL_DEV_CAP_HDM, expected);
+	set_bit(CXL_DEV_CAP_RAS, expected);
+
+	rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlmds, found);
+	if (rc) {
+		pci_err(pci_dev, "CXL accel setup regs failed");
+		goto err_regs;
+	}
+
+	/*
+	 * Checking mandatory caps are there as, at least, a subset of those
+	 * found.
+	 */
+	if (!bitmap_subset(expected, found, CXL_MAX_CAPS)) {
+		pci_err(pci_dev,
+			"CXL device capabilities found(%pb) not as expected(%pb)",
+			found, expected);
+		rc = -EIO;
+		goto err_regs;
+	}
+
 	probe_data->cxl = cxl;
 
 	return 0;
+
+err_regs:
+	kfree(probe_data->cxl);
+	return rc;
+
 }
 
 void efx_cxl_exit(struct efx_probe_data *probe_data)