| Message ID | 20250226075449.136544-2-quic_mmanikan@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show
Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com
[205.220.180.131])
(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
(No client certificate requested)
by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67C18224257;
Wed, 26 Feb 2025 07:55:42 +0000 (UTC)
Authentication-Results: smtp.subspace.kernel.org;
arc=none smtp.client-ip=205.220.180.131
ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;
t=1740556544; cv=none;
b=AxjqDiw4q/8K4Os7TNalIoCrzqGw7LDFO4YNAwQ9+xzTrOHDCR7keDMzC5ZGN9TzUMvL/SeMPlQpJT9rceOEJb3WM5SOIbr6vcekv1mP2QvjAUtxRzMgcu3/IS1r4K60DcC8KRG4GRowOhr2BCa7tJa3t8PBX/0sV1xm2VRuNiQ=
ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org;
s=arc-20240116; t=1740556544; c=relaxed/simple;
bh=a0/e1T258a4ao7AZUdNyyCcRIHXnm7dAXHww8HOo71E=;
h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:
MIME-Version:Content-Type;
b=Sl0w3HueQfKhM831ix7HKTYp55JHGKDzXInUu9cpysiMQy1I8H909p+/TXJ/brIRkekMeGSa7ZUad3uBlvhg0hEi3WMDb8pobTsxGKR7uxUt9i3zRxv0EwibKPXQXS0z/JX9ENl/on5ginNEsiZZLQeuRo3fpseR3Ae5PJMQwIM=
ARC-Authentication-Results: i=1; smtp.subspace.kernel.org;
dmarc=pass (p=none dis=none) header.from=quicinc.com;
spf=pass smtp.mailfrom=quicinc.com;
dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com
header.b=US/c9j3I; arc=none smtp.client-ip=205.220.180.131
Authentication-Results: smtp.subspace.kernel.org;
dmarc=pass (p=none dis=none) header.from=quicinc.com
Authentication-Results: smtp.subspace.kernel.org;
spf=pass smtp.mailfrom=quicinc.com
Authentication-Results: smtp.subspace.kernel.org;
dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com
header.b="US/c9j3I"
Received: from pps.filterd (m0279872.ppops.net [127.0.0.1])
by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id
51PMWqjN011850;
Wed, 26 Feb 2025 07:55:17 GMT
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=
cc:content-transfer-encoding:content-type:date:from:in-reply-to
:message-id:mime-version:references:subject:to; s=qcppdkim1; bh=
IdRqAT7mr3YitPfVTDI/bJSioG2RbZVR/XaLztOHiCc=; b=US/c9j3Ilw2WFU22
VlDNBVg5pbtNZlBTrI6z/2w5ZMBvVPoJxSq4zglLY1zrm+w8l2UDaaZpvxpMve/Z
f4Fhzno46CHLOtMHQYQzJb1APLaWyP2z8OOBkLKHCrkHIQoFzLycYHvAAd7UyO88
1dZp5k3I+qV7tmyhTzIjFZ5Ld+8YAVWOT8irNRNY9IfQYP7COozrDNATx1SAAAfb
EfDkY8Ss9jHkB3+JB7Hg9n3XHWKy7gmPPy8O0fOftPVF/tpAi6O63JC9WUqJ5cqP
nC2LCSfVD5g9v9uVxD244tqvFVuABP3FwbMNzPaB+whxEFjL3rPLK4nw4AnXa6Kv
h5WRdQ==
Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com
[199.106.103.254])
by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 451prk96hu-1
(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);
Wed, 26 Feb 2025 07:55:17 +0000 (GMT)
Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com
[10.46.141.250])
by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id
51Q7tGtX012970
(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);
Wed, 26 Feb 2025 07:55:16 GMT
Received: from hu-mmanikan-blr.qualcomm.com (10.80.80.8) by
nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server
(version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id
15.2.1544.9; Tue, 25 Feb 2025 23:55:07 -0800
From: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
To: <andersson@kernel.org>, <mturquette@baylibre.com>, <sboyd@kernel.org>,
<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<konradybcio@kernel.org>, <catalin.marinas@arm.com>,
<will@kernel.org>,
<p.zabel@pengutronix.de>, <richardcochran@gmail.com>,
<geert+renesas@glider.be>, <dmitry.baryshkov@linaro.org>,
<arnd@arndb.de>, <nfraprado@collabora.com>, <quic_tdas@quicinc.com>,
<biju.das.jz@bp.renesas.com>, <ebiggers@google.com>,
<ross.burton@arm.com>, <elinor.montmasson@savoirfairelinux.com>,
<quic_anusha@quicinc.com>, <linux-arm-msm@vger.kernel.org>,
<linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<netdev@vger.kernel.org>
CC: <quic_srichara@quicinc.com>, <quic_varada@quicinc.com>
Subject: [PATCH v11 1/6] dt-bindings: clock: gcc-ipq9574: Add definition for
GPLL0_OUT_AUX
Date: Wed, 26 Feb 2025 13:24:44 +0530
Message-ID: <20250226075449.136544-2-quic_mmanikan@quicinc.com>
X-Mailer: git-send-email 2.34.1
In-Reply-To: <20250226075449.136544-1-quic_mmanikan@quicinc.com>
References: <20250226075449.136544-1-quic_mmanikan@quicinc.com>
Precedence: bulk
X-Mailing-List: netdev@vger.kernel.org
List-Id: <netdev.vger.kernel.org>
List-Subscribe: <mailto:netdev+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:netdev+unsubscribe@vger.kernel.org>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To
nasanex01b.na.qualcomm.com (10.46.141.250)
X-QCInternal: smtphost
X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800
signatures=585085
X-Proofpoint-GUID: nevgTaBvKrs-9CYj0wM7OUvDX2iCV_d0
X-Proofpoint-ORIG-GUID: nevgTaBvKrs-9CYj0wM7OUvDX2iCV_d0
X-Proofpoint-Virus-Version: vendor=baseguard
engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34
definitions=2025-02-26_01,2025-02-26_01,2024-11-22_01
X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0
suspectscore=0 mlxscore=0
bulkscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 malwarescore=0
impostorscore=0 adultscore=0 priorityscore=1501 spamscore=0
mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1
engine=8.19.0-2502100000 definitions=main-2502260062
|
| Series |
Add NSS clock controller support for IPQ9574
|
expand
|
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Not a local patch |
diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index f238aa4794a8..0e7c319897f3 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -202,4 +202,5 @@ #define GCC_PCIE1_PIPE_CLK 211 #define GCC_PCIE2_PIPE_CLK 212 #define GCC_PCIE3_PIPE_CLK 213 +#define GPLL0_OUT_AUX 214 #endif