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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Saeed Mahameed , Gal Pressman , "Leon Romanovsky" , Michal Swiatkowski , Leon Romanovsky , Tariq Toukan , , , , Amir Tzin , Mark Bloch Subject: [PATCH net-next V2 4/6] net/mlx5: Lag, Enable Multiport E-Switch offloads on 8 ports LAG Date: Tue, 4 Mar 2025 18:06:18 +0200 Message-ID: <20250304160620.417580-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250304160620.417580-1-tariqt@nvidia.com> References: <20250304160620.417580-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A0:EE_|SA3PR12MB7902:EE_ X-MS-Office365-Filtering-Correlation-Id: dadce33a-d0e1-477b-9a6d-08dd5b36a25c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: 6vk0V2UcY6tqDXBV6Ir0WPv1SwgZsIScWOGaZRkgrJZrrTjFirrFkxezx4MZzfK63krc/S56FSjakiYqtoQjGCDWk2j8so+sI3tSK2vBl23NNeN98Cs+2X/y0rIdIoTmQ/0coHvq9sUcnNuui05AMY9vNrJ0a+YJS2T4p5OYps7qn7TtfpXP/0Vz6uFxhbIr8zqJ9V77mVnepD5jtSPl/T5S83S/aivAe8eCz4B+dd+nO0CJmAGA60QaRxY0r8GPFGi49WTR+mvieop/StCB6RsMBmV1Y5P/v2p6cdgj3nQIawmjsuu3n4GPI1al8zEaMTmQp5NED1rWsCrPHp40o8zex5Wdcx5Ky2/S56jmRFZRZ/YqS+sD1rh1e22FIjFpHJgdW0X92ScMKSerxAexCJEJEMm15HzxcD/J8dl1VWKdXhanIV++trsWExQ6669wjLZCt5TA8/z+qsMIns7m/yeVw9RPFWF9U3hsqybWKBh9bgdKIMcnd7OsktHP+gAxGK3xmHyaead5BCIN8U4TDFPDtkmD1Rxla3Tato5mMmpdQ/PpR/x/S3qqxRke2HviR19NpnurGia6lpxZxf0E7/KOUoTcjMfbF05bS8Qp81ZRTlFJ1TWcOQJdoEEDuAGyL8Kb932KifR+RlPi5ZrV2CInpDV1CbGmr9HRoOnBytkQc5RV6nKQOHainQbDQA7YHtaeMZVoZk1qWy+hxsTVFEm3LQDngCBYXkqra5TByhNCEctjQtGWJSrzozIMxwqOKg3RcHCrYLTAS/Oy5Ae4FS9VcwyvDq3qG+H8acF68uuxghHoBFqc5DwS9YYMk5P5hjI8pOBnefaGbBp1Dh4nn0WwVzfxemY5nZwHPlLkbxraqp0PDKF5dL6gN2SadWO90P78n+KA5Ts70xar7MZscUCxvOr085ZujVWG0VP1DPsZ/ejtCu40jjvK25FEZ9NrnQQ1y1TAoAia3N5xYd9Io679ekSbU4xR1EXRR56dnP4BffSgRgXp7dEjPPR7d6utkHKq+UR9W1+O6xvfB5mZ91VGb1uxJiJg5LUy53o5iTeLxUOI/szwkpBQ0+DjNjl8FW5J0iKlEVx359MrXFnVxZv+CqVeFYqlT+cQ+StyeVMF23yBSp71521XaQI2m8DpCnui/iRcI03CmwAmbZBGb9RONPn0pnRwCOxyYqFBofx/v3LjRm60eu1u7ZAhjDH/DHJNqJgeHaF5Xxyi/JABkCyA3eFHhfqy7X5JtviEQGUtadOXrc9Q4PGzppGnn5ycyLwVggK16afaft5avwnD9hMnyL0OTi1eX01sVXUd1G1Kfass6ccIuvzsYkwH5Z2PRYNgEt57aDzlb1JI7LGcuzhyHVOtZhgnlyGt3fzNjFirBa2MBjykRHMKMqjRbGX/n6jefUv7AA1I3LTYUBVYaHbKOrJBBCc/+o1KmyaVA/+gFtsdjjdKunSBAdV0aT6npcAJq1UDcy8+gWQV730RIWWN+7FjVdKOBlTHuZfjL7Y= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2025 16:07:16.5255 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dadce33a-d0e1-477b-9a6d-08dd5b36a25c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7902 X-Patchwork-Delegate: kuba@kernel.org From: Amir Tzin Patch [1] added mlx5 driver support for 8 ports HCAs which are available since ConnectX-8. Now that Multiport E-Switch is tested, we can enable it by removing flag MLX5_LAG_MPESW_OFFLOADS_SUPPORTED_PORTS. [1] commit e0e6adfe8c20 ("net/mlx5: Enable 8 ports LAG") Signed-off-by: Amir Tzin Signed-off-by: Mark Bloch Signed-off-by: Tariq Toukan Reviewed-by: Michal Swiatkowski --- drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c index ffac0bd6c895..cbde54324059 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/mpesw.c @@ -65,7 +65,6 @@ static int mlx5_mpesw_metadata_set(struct mlx5_lag *ldev) return err; } -#define MLX5_LAG_MPESW_OFFLOADS_SUPPORTED_PORTS 4 static int enable_mpesw(struct mlx5_lag *ldev) { int idx = mlx5_lag_get_dev_index_by_seq(ldev, MLX5_LAG_P1); @@ -77,9 +76,6 @@ static int enable_mpesw(struct mlx5_lag *ldev) return -EINVAL; dev0 = ldev->pf[idx].dev; - if (ldev->ports > MLX5_LAG_MPESW_OFFLOADS_SUPPORTED_PORTS) - return -EOPNOTSUPP; - if (mlx5_eswitch_mode(dev0) != MLX5_ESWITCH_OFFLOADS || !MLX5_CAP_PORT_SELECTION(dev0, port_select_flow_table) || !MLX5_CAP_GEN(dev0, create_lag_when_not_master_up) ||