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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Danielle Ratson , Petr Machata , Ido Schimmel , Amit Cohen , , Jiri Pirko Subject: [PATCH net 3/5] mlxsw: pci: Sync Rx buffers for device Date: Fri, 25 Oct 2024 16:26:27 +0200 Message-ID: <92e01f05c4f506a4f0a9b39c10175dcc01994910.1729866134.git.petrm@nvidia.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB59:EE_|SJ2PR12MB7992:EE_ X-MS-Office365-Filtering-Correlation-Id: 96cd0c79-9189-4463-f0f5-08dcf50125c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: Q2MBzRIYWInXbKcfvcLmFcQC3pP1adkTQ8NNc/kc0IOudHQt9uJu/bZyQSe9OAmnJptfQUVOZaK9pZAlHQ+uk6RfzPWvC68gJtgLKGAZhW4T8h/UUW1Sm8Z/CtQ5penE+WAgwBXRNL3fXwmcNWdmcZNv5NpAeHUIY6hgmJ/YSXXWCYskSV4yaw/dZO954j3dPk9QemUAuvdK7dX1JKSMIP5Vxi8b+8E6W/ahsXuhUDyFFzWZqEhlVpf/8vkzvtfHm2Qcv/IN9WQFfzmXYMO3rRqdbqtSBRlLPbIixnjt/6rMdQnK/LaNZjq5bROuErN+sz3+1lEd+0rbRFkMfRy85Euv5oGMMN/WzazLP+j5gjcRNlcnZiu1j5CctlA89fawlYaJlB8gwIwhaWGO+nT1aeiYQXXr6TyPivE7a3kSQZRwQgXcTnCA74hceNnk5ylfSaZMl9oj7NQPhd24kqknUaoWmeg3wyUKDfvw7f4fPj7hsUTiYEfTBlZ8llyNxhxqMrUlt2IHp9LsNNQraClfrQFoaDp6D68AruqgBal9YO2PdYqNUWFz/rvThaqSvZlo7GtMe8wXAPtmAoQjtAOAvEtjscFcEeX6/zrYtB6e15mRNTlwJYIOIh5YeCB72pIXfEMvqU2DSLvDRZ3v/VoEwK9yCMoTx1VJS6BUonB8rUbaW9pvfgGCIj21dZwRBCp2TuybYIrmBrOZNq1Nj7SzSziSDHToYa10zuj8EvISiuDJrryfAa0NFdzn2Yub1yWIuVi/iBRWBWow1gIHO5W7ixRWsKrO16myWekR1fuhmLTNCpy1gXhRGLD32vO5sMctyXZMsuNPNk7yrVYVihLuMSbg0VVpJhAPz7yyegkgkUYFSdH344RA1lUGI7wwebJ33720GGywtpbLbR9WQDrkT0KwsrEiz8w45PGpr8IuI38c+amuipizSpdxNBvzWpic1Ca/wANv+112f1Vtoj4I8hck7pVpWumnIlu0SLqcLLCk76NxLF0s9XJFHiQA454TUPb5WhhPNFyXADWJXomwCcMbgIQb8pCzVZIoHxZEYyuZPTKn3i63FZdMw10qFR602Rs1WxbRlzqx3Bv/y4ZEVD7+D9pNGRVfOfe9PAVt+cwjuhRhx1wYrg7DW/SfKXSV3RDeNagf8QOaZCdi0hk4w4qP00eTL13HtgcLicfEPkjhAKN3NtUlYKvAVu5RVw4GqvjW3BcRJFIAulboKGaCAE57gm3pcqdc7gmiCw6tEBw3YKaZzfw+ADPsTNlwmXFWqmb2iqy08yro2wa3ieByLJdqR+tnsOfMLyi38K91Y+qJVZnrjuQsJAiZ3SXYSCKj/m7H6W1uHq8D00flzhpIrGZm7CP9ad6UaY7KYQWgo1ZqK9t10SeijjKQWBtpcEPsk89gaJ8iZd227nueCtM1mA== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 14:27:25.5303 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96cd0c79-9189-4463-f0f5-08dcf50125c6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB59.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7992 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen Non-coherent architectures, like ARM, may require invalidating caches before the device can use the DMA mapped memory, which means that before posting pages to device, drivers should sync the memory for device. Sync for device can be configured as page pool responsibility. Set the relevant flag and define max_len for sync. Cc: Jiri Pirko Fixes: b5b60bb491b2 ("mlxsw: pci: Use page pool for Rx buffers allocation") Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 2320a5f323b4..d6f37456fb31 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -996,12 +996,13 @@ static int mlxsw_pci_cq_page_pool_init(struct mlxsw_pci_queue *q, if (cq_type != MLXSW_PCI_CQ_RDQ) return 0; - pp_params.flags = PP_FLAG_DMA_MAP; + pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; pp_params.pool_size = MLXSW_PCI_WQE_COUNT * mlxsw_pci->num_sg_entries; pp_params.nid = dev_to_node(&mlxsw_pci->pdev->dev); pp_params.dev = &mlxsw_pci->pdev->dev; pp_params.napi = &q->u.cq.napi; pp_params.dma_dir = DMA_FROM_DEVICE; + pp_params.max_len = PAGE_SIZE; page_pool = page_pool_create(&pp_params); if (IS_ERR(page_pool))