| Message ID | AM9PR04MB8506A4B49180F34117B93655E2832@AM9PR04MB8506.eurprd04.prod.outlook.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | Add support for Synopsis DWMAC IP on NXP Automotive SoCs S32G2xx/S32G3xx/S32R45 | expand |
On 8/18/2024 2:50 PM, Jan Petrous (OSS) wrote: > Add support for CSR clock range up to 800 MHz. > > When in, fix STMMAC_CSR_250_300M divider comment. > The phrasing of this was somewhat confusing. I would also have chosen to do this as a separate fix, since it makes reading the change somewhat more difficult. A separate change could also explain how it was wrong in the first place and add more context. Either way, I think its a minor enough change and it only affects a code comment. Not a huge deal. Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
On Tue, Aug 20, 2024 at 02:09:56PM -0700, Jacob Keller wrote: > > > On 8/18/2024 2:50 PM, Jan Petrous (OSS) wrote: > > Add support for CSR clock range up to 800 MHz. > > > > When in, fix STMMAC_CSR_250_300M divider comment. > > > > The phrasing of this was somewhat confusing. I would also have chosen to > do this as a separate fix, since it makes reading the change somewhat > more difficult. A separate change could also explain how it was wrong in > the first place and add more context. OK, divided to the two commits for v3. > > Either way, I think its a minor enough change and it only affects a code > comment. Not a huge deal. > > Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Thanks you. /Jan
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h index cd36ff4da68c..e90d3c5ac917 100644 --- a/drivers/net/ethernet/stmicro/stmmac/common.h +++ b/drivers/net/ethernet/stmicro/stmmac/common.h @@ -256,6 +256,8 @@ struct stmmac_safety_stats { #define CSR_F_150M 150000000 #define CSR_F_250M 250000000 #define CSR_F_300M 300000000 +#define CSR_F_500M 500000000 +#define CSR_F_800M 800000000 #define MAC_CSR_H_FRQ_MASK 0x20 diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index f3a1b179aaea..ac80d8a2b743 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -324,6 +324,10 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv) priv->clk_csr = STMMAC_CSR_150_250M; else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) priv->clk_csr = STMMAC_CSR_250_300M; + else if ((clk_rate >= CSR_F_300M) && (clk_rate < CSR_F_500M)) + priv->clk_csr = STMMAC_CSR_300_500M; + else if ((clk_rate >= CSR_F_500M) && (clk_rate < CSR_F_800M)) + priv->clk_csr = STMMAC_CSR_500_800M; } if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) { diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index 84e13bd5df28..7caaa5ae6674 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -33,7 +33,9 @@ #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ -#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ +#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/124 */ +#define STMMAC_CSR_300_500M 0x6 /* MDC = clk_scr_i/204 */ +#define STMMAC_CSR_500_800M 0x7 /* MDC = clk_scr_i/324 */ /* MTL algorithms identifiers */ #define MTL_TX_ALGORITHM_WRR 0x0
Add support for CSR clock range up to 800 MHz. When in, fix STMMAC_CSR_250_300M divider comment. Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> --- drivers/net/ethernet/stmicro/stmmac/common.h | 2 ++ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 ++++ include/linux/stmmac.h | 4 +++- 3 files changed, 9 insertions(+), 1 deletion(-)