From patchwork Mon Sep 9 07:46:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WangYuli X-Patchwork-Id: 13796229 Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C36471B0101 for ; Mon, 9 Sep 2024 07:48:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=18.194.254.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725868094; cv=none; b=T6/GLG4v3R0PVdHVMLu7s1s+rKfYflpOjTO6el/7Aw9GmHUoFF5rBafxNBiLdN7J7onYAE5c2UZkDocitnkBuc7M9wa7qPTP2kQ4e6k6fdD4Ougyv3gzBVIpnd/46bo+uWVOt5LTPSsP0Y2K+FwV60d2MHL/cRA56kPMFWMNp14= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725868094; c=relaxed/simple; bh=cvqm85HxZws8m0ffPbvyp+Zw+eEM2Dc4RD3F3vWaoqQ=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=a/B7IuYahVqPErd1Kj5osQqfxNuChAi3ZY80lvtKSVbMiSSxg7f06+/lPfwMt6acalkKhswZFbTArW4qc0kF6s1X6SBZFDF2Q94RP8V4h6nGfhvqftdj+EOe49li6ADENU77hdx70iVVa2MDZQYfakqcYBwkuX0peq9PKNkWB2E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=uniontech.com; spf=pass smtp.mailfrom=uniontech.com; dkim=pass (1024-bit key) header.d=uniontech.com header.i=@uniontech.com header.b=AK6aZCuK; arc=none smtp.client-ip=18.194.254.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=uniontech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=uniontech.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=uniontech.com header.i=@uniontech.com header.b="AK6aZCuK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=uniontech.com; s=onoh2408; t=1725868028; bh=prMGJ3mMUTIxkfIlbBVGa2TBtFoTvRzNWFckIJQYeCI=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=AK6aZCuKgMo2Ixy8o6QqNspmk662kCglPvIF4ZcWFXXkSY3fEt21LcH+jXJ64F4+o y/KqanIVzuQ/YxFXwX4EjF3WYQsXScuqTXT+hZ2SGsXZHuzV9zoWiLEhqYzPSJMgHU Gcb5RTkxhBCcn8ym66dpAlapAZlb7+EKuOswOLWA= X-QQ-mid: bizesmtpsz13t1725868011tpw342 X-QQ-Originating-IP: NHWKxukEJ5SZHvLWpkrfTWlhEG3Mlt8ERQZDBoe249Q= Received: from localhost.localdomain ( [113.57.152.160]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 09 Sep 2024 15:46:48 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 1 X-BIZMAIL-ID: 17961958660430279513 From: WangYuli To: stable@vger.kernel.org, gregkh@linuxfoundation.org, sashal@kernel.org, william.qiu@starfivetech.com, emil.renner.berthing@canonical.com, conor.dooley@microchip.com, wangyuli@uniontech.com, xingyu.wu@starfivetech.com, walker.chen@starfivetech.com, robh@kernel.org, hal.feng@starfivetech.com Cc: kernel@esmil.dk, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, richardcochran@gmail.com, netdev@vger.kernel.org Subject: [PATCH 6.6 1/4] riscv: dts: starfive: add assigned-clock* to limit frquency Date: Mon, 9 Sep 2024 15:46:27 +0800 Message-ID: X-Mailer: git-send-email 2.43.4 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtpsz:uniontech.com:qybglogicsvrgz:qybglogicsvrgz8a-1 From: William Qiu In JH7110 SoC, we need to go by-pass mode, so we need add the assigned-clock* properties to limit clock frquency. Signed-off-by: William Qiu Reviewed-by: Emil Renner Berthing Signed-off-by: Conor Dooley Signed-off-by: WangYuli --- .../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 062b97c6e7df..4874e3bb42ab 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -204,6 +204,8 @@ &i2c6 { &mmc0 { max-frequency = <100000000>; + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; + assigned-clock-rates = <50000000>; bus-width = <8>; cap-mmc-highspeed; mmc-ddr-1_8v; @@ -220,6 +222,8 @@ &mmc0 { &mmc1 { max-frequency = <100000000>; + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; + assigned-clock-rates = <50000000>; bus-width = <4>; no-sdio; no-mmc;