diff mbox series

[net-next,2/2] net: phy: marvell: configure RGMII delays for 88E1118

Message ID E1n4mpH-002PKK-37@rmk-PC.armlinux.org.uk (mailing list archive)
State Accepted
Commit f22725c95ececb703c3f741e8f946d23705630b7
Delegated to: Netdev Maintainers
Headers show
Series Fix RGMII delays for 88E1118 | expand

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Context Check Description
netdev/tree_selection success Clearly marked for net-next
netdev/fixes_present success Fixes tag not required for -next series
netdev/subject_prefix success Link
netdev/cover_letter success Series has a cover letter
netdev/patch_count success Link
netdev/header_inline success No static functions without inline keyword in header files
netdev/build_32bit success Errors and warnings before: 0 this patch: 0
netdev/cc_maintainers warning 1 maintainers not CCed: linux@armlinux.org.uk
netdev/build_clang success Errors and warnings before: 0 this patch: 0
netdev/module_param success Was 0 now: 0
netdev/verify_signedoff success Signed-off-by tag matches author and committer
netdev/verify_fixes success No Fixes tag
netdev/build_allmodconfig_warn success Errors and warnings before: 0 this patch: 0
netdev/checkpatch success total: 0 errors, 0 warnings, 0 checks, 12 lines checked
netdev/kdoc success Errors and warnings before: 0 this patch: 0
netdev/source_inline success Was 0 now: 0

Commit Message

Russell King (Oracle) Jan. 4, 2022, 4:38 p.m. UTC 
Corentin Labbe reports that the SSI 1328 does not work when allowing
the PHY to operate at gigabit speeds, but does work with the generic
PHY driver.

This appears to be because m88e1118_config_init() writes a fixed value
to the MSCR register, claiming that this is to enable 1G speeds.
However, this always sets bits 4 and 5, enabling RGMII transmit and
receive delays. The suspicion is that the original board this was
added for required the delays to make 1G speeds work.

Add the necessary configuration for RGMII delays for the 88E1118 to
bring this into line with the requirements for RGMII support, and thus
make the SSI 1328 work.

Corentin Labbe has tested this on gemini-ssi1328 and gemini-ns2502.

Reported-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
 drivers/net/phy/marvell.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Andrew Lunn Jan. 4, 2022, 4:45 p.m. UTC | #1 
On Tue, Jan 04, 2022 at 04:38:19PM +0000, Russell King (Oracle) wrote:
> Corentin Labbe reports that the SSI 1328 does not work when allowing
> the PHY to operate at gigabit speeds, but does work with the generic
> PHY driver.
> 
> This appears to be because m88e1118_config_init() writes a fixed value
> to the MSCR register, claiming that this is to enable 1G speeds.
> However, this always sets bits 4 and 5, enabling RGMII transmit and
> receive delays. The suspicion is that the original board this was
> added for required the delays to make 1G speeds work.
> 
> Add the necessary configuration for RGMII delays for the 88E1118 to
> bring this into line with the requirements for RGMII support, and thus
> make the SSI 1328 work.
> 
> Corentin Labbe has tested this on gemini-ssi1328 and gemini-ns2502.
> 
> Reported-by: Corentin Labbe <clabbe.montjoie@gmail.com>
> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew
diff mbox series

Patch

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 64e7874c95f4..739859c0dfb1 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -1234,6 +1234,12 @@  static int m88e1118_config_init(struct phy_device *phydev)
 	if (err < 0)
 		return err;
 
+	if (phy_interface_is_rgmii(phydev)) {
+		err = m88e1121_config_aneg_rgmii_delays(phydev);
+		if (err < 0)
+			return err;
+	}
+
 	/* Adjust LED Control */
 	if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
 		leds = 0x1100;